ARM Packages: Removed trailing spaces

[mirror_edk2.git] / ArmPkg / Library / ArmLib / Arm9 / Arm9Support.asm

diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm b/ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm
index fc87828e202789ba0dff12676394903f25bc7ce7..4aaa546ca0c8acdec0413b49101465b5894fe7ad 100644 (file)
--- a/ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm
+++ b/ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm
@@ -1,4 +1,4 @@
-//------------------------------------------------------------------------------ \r
+//------------------------------------------------------------------------------\r
 //\r
 // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
 //\r
@@ -41,12 +41,12 @@ IC_ON       EQU     ( 0x1:SHL:12 )
 \r
 \r
 ArmInvalidateDataCacheEntryByMVA\r
-  MCR     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line                                           \r
+  MCR     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line\r
   BX      lr\r
 \r
 \r
 ArmCleanDataCacheEntryByMVA\r
-  MCR     p15, 0, r0, c7, c10, 1  ; clean single data cache line     \r
+  MCR     p15, 0, r0, c7, c10, 1  ; clean single data cache line\r
   BX      lr\r
 \r
 \r
@@ -60,7 +60,7 @@ ArmEnableInstructionCache
   ORR     R0,R0,R1             ;Set I bit\r
   MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data\r
   BX      LR\r
-  \r
+\r
 ArmDisableInstructionCache\r
   LDR     R1,=IC_ON\r
   MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data\r
@@ -100,7 +100,7 @@ ArmEnableDataCache
   ORR     R0,R0,R1              ;Set C bit\r
   MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data\r
   BX      LR\r
-    \r
+\r
 ArmDisableDataCache\r
   LDR     R1,=DC_ON\r
   MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data\r
@@ -121,7 +121,7 @@ ArmInvalidateDataCache
   MOV     R0,#0\r
   MCR     p15,0,R0,c7,c10,4     ;Drain write buffer\r
   BX      LR\r
-  \r
+\r
 ArmCleanInvalidateDataCache\r
   MRC     p15,0,r15,c7,c14,3\r
   BNE     ArmCleanInvalidateDataCache\r
@@ -139,12 +139,12 @@ ASM_PFX(ArmDataMemoryBarrier):
   mov R0, #0\r
   mcr P15, #0, R0, C7, C10, #5  ; Check to see if this is correct\r
   bx      LR\r
-  \r
+\r
 ASM_PFX(ArmDataSyncronizationBarrier):\r
   mov R0, #0\r
   mcr P15, #0, R0, C7, C10, #4 ; Check to see if this is correct\r
   bx      LR\r
-  \r
+\r
 ASM_PFX(ArmInstructionSynchronizationBarrier):\r
   MOV R0, #0\r
   MCR P15, #0, R0, C7, C5, #4 ; Check to see if this is correct\r