ARM Packages: Removed trailing spaces

[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmV7 / ArmV7Support.S

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
index 954762717c50cf6bccbd1e23c378bd61980ec077..c31d49bcfb01c04912c4647a028af5421abc4aeb 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
@@ -1,4 +1,4 @@
-#------------------------------------------------------------------------------ \r
+#------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
 # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
@@ -63,13 +63,13 @@ GCC_ASM_EXPORT (ArmReadIdPfr1)
 \r
 \r
 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):\r
-  mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line       \r
+  mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line\r
   dsb\r
   isb\r
   bx      lr\r
 \r
 ASM_PFX(ArmCleanDataCacheEntryByMVA):\r
-  mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line     \r
+  mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line\r
   dsb\r
   isb\r
   bx      lr\r
@@ -83,21 +83,21 @@ ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
 \r
 \r
 ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):\r
-  mcr     p15, 0, r0, c7, c6, 2        @ Invalidate this line    \r
+  mcr     p15, 0, r0, c7, c6, 2        @ Invalidate this line\r
   dsb\r
   isb\r
   bx      lr\r
 \r
 \r
 ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):\r
-  mcr     p15, 0, r0, c7, c14, 2       @ Clean and Invalidate this line    \r
+  mcr     p15, 0, r0, c7, c14, 2       @ Clean and Invalidate this line\r
   dsb\r
   isb\r
   bx      lr\r
 \r
 \r
 ASM_PFX(ArmCleanDataCacheEntryBySetWay):\r
-  mcr     p15, 0, r0, c7, c10, 2       @ Clean this line    \r
+  mcr     p15, 0, r0, c7, c10, 2       @ Clean this line\r
   dsb\r
   isb\r
   bx      lr\r
@@ -141,7 +141,7 @@ ASM_PFX(ArmDisableCachesAndMmu):
 ASM_PFX(ArmMmuEnabled):\r
   mrc     p15,0,R0,c1,c0,0\r
   and     R0,R0,#1\r
-  bx      LR  \r
+  bx      LR\r
 \r
 ASM_PFX(ArmEnableDataCache):\r
   ldr     R1,=DC_ON\r
@@ -151,7 +151,7 @@ ASM_PFX(ArmEnableDataCache):
   dsb\r
   isb\r
   bx      LR\r
-    \r
+\r
 ASM_PFX(ArmDisableDataCache):\r
   ldr     R1,=DC_ON\r
   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data\r
@@ -169,7 +169,7 @@ ASM_PFX(ArmEnableInstructionCache):
   dsb\r
   isb\r
   bx      LR\r
-  \r
+\r
 ASM_PFX(ArmDisableInstructionCache):\r
   ldr     R1,=IC_ON\r
   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data\r
@@ -225,14 +225,14 @@ ASM_PFX(ArmV7AllDataCachesOperation):
   beq   L_Finished\r
   mov   R10, #0\r
 \r
-Loop1:   \r
+Loop1:\r
   add   R2, R10, R10, LSR #1  @ Work out 3xcachelevel\r
   mov   R12, R6, LSR R2       @ bottom 3 bits are the Cache type for this level\r
   and   R12, R12, #7          @ get those 3 bits alone\r
   cmp   R12, #2\r
   blt   L_Skip                  @ no cache or only instruction cache at this level\r
   mcr   p15, 2, R10, c0, c0, 0  @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r
-  isb                           @ isb to sync the change to the CacheSizeID reg \r
+  isb                           @ isb to sync the change to the CacheSizeID reg\r
   mrc   p15, 1, R12, c0, c0, 0  @ reads current Cache Size ID register (CCSIDR)\r
   and   R2, R12, #0x7           @ extract the line length field\r
   add   R2, R2, #4              @ add 4 for the line length offset (log2 16 bytes)\r
@@ -246,10 +246,10 @@ Loop1:
   sub   R7, R7, #1\r
   ands  R7, R7, R12, LSR #13    @ R7 is the max number of the index size (right aligned)\r
 \r
-Loop2:   \r
+Loop2:\r
   mov   R9, R4                  @ R9 working copy of the max way size (right aligned)\r
 \r
-Loop3:   \r
+Loop3:\r
   orr   R0, R10, R9, LSL R5     @ factor in the way number and cache number into R11\r
   orr   R0, R0, R7, LSL R2      @ factor in the index number\r
 \r
@@ -259,11 +259,11 @@ Loop3:
   bge   Loop3\r
   subs  R7, R7, #1              @ decrement the index\r
   bge   Loop2\r
-L_Skip:  \r
+L_Skip:\r
   add   R10, R10, #2            @ increment the cache number\r
   cmp   R3, R10\r
   bgt   Loop1\r
-  \r
+\r
 L_Finished:\r
   dsb\r
   ldmfd SP!, {r4-r12, lr}\r
@@ -285,7 +285,7 @@ Loop4:
   cmp   R12, #2\r
   blt   Skip2                   @ no cache or only instruction cache at this level\r
   mcr   p15, 2, R10, c0, c0, 0  @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r
-  isb                           @ isb to sync the change to the CacheSizeID reg \r
+  isb                           @ isb to sync the change to the CacheSizeID reg\r
   mrc   p15, 1, R12, c0, c0, 0  @ reads current Cache Size ID register (CCSIDR)\r
   and   R2, R12, #0x7            @ extract the line length field\r
   add   R2, R2, #4              @ add 4 for the line length offset (log2 16 bytes)\r
@@ -312,7 +312,7 @@ Skip2:
   add   R10, R10, #2            @ increment the cache number\r
   cmp   R3, R10\r
   bgt   Loop4\r
-  \r
+\r
 Finished2:\r
   dsb\r
   ldmfd SP!, {r4-r12, lr}\r
@@ -321,12 +321,12 @@ Finished2:
 ASM_PFX(ArmDataMemoryBarrier):\r
   dmb\r
   bx      LR\r
-  \r
+\r
 ASM_PFX(ArmDataSyncronizationBarrier):\r
 ASM_PFX(ArmDrainWriteBuffer):\r
   dsb\r
   bx      LR\r
-  \r
+\r
 ASM_PFX(ArmInstructionSynchronizationBarrier):\r
   isb\r
   bx      LR\r
@@ -338,7 +338,7 @@ ASM_PFX(ArmReadVBar):
 \r
 ASM_PFX(ArmWriteVBar):\r
   # Set the Address of the Vector Table in the VBAR register\r
-  mcr     p15, 0, r0, c12, c0, 0 \r
+  mcr     p15, 0, r0, c12, c0, 0\r
   # Ensure the SCTLR.V bit is clear\r
   mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r
   bic     r0, r0, #0x00002000   @ clear V bit\r
@@ -376,7 +376,7 @@ ASM_PFX(ArmInvalidateInstructionAndDataTlb):
 ASM_PFX(ArmReadMpidr):\r
   mrc     p15, 0, r0, c0, c0, 5       @ read MPIDR\r
   bx      lr\r
-  \r
+\r
 ASM_PFX(ArmReadTpidrurw):\r
   mrc     p15, 0, r0, c13, c0, 2    @ read TPIDRURW\r
   bx      lr\r