ArmPkg/ArmLib: switch to ASM_FUNC() asm macro

[mirror_edk2.git] / ArmPkg / Library / ArmLib / Common / AArch64 / ArmLibSupport.S

diff --git a/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S
index c9f3bd1e8810e10fbd2f01a27130fdd683525816..9d3dd66b10eb85f76933981b8654b9b3abb1f3f7 100644 (file)
--- a/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S
+++ b/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S
@@ -2,6 +2,7 @@
 #\r
 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
 # Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.\r
+# Copyright (c) 2016, Linaro Limited. All rights reserved.\r
 #\r
 # This program and the accompanying materials\r
 # are licensed and made available under the terms and conditions of the BSD License\r
@@ -15,76 +16,48 @@
 \r
 #include <AsmMacroIoLibV8.h>\r
 \r
-.text\r
-.align 3\r
-GCC_ASM_EXPORT (ArmReadMidr)\r
-GCC_ASM_EXPORT (ArmCacheInfo)\r
-GCC_ASM_EXPORT (ArmGetInterruptState)\r
-GCC_ASM_EXPORT (ArmGetFiqState)\r
-GCC_ASM_EXPORT (ArmGetTTBR0BaseAddress)\r
-GCC_ASM_EXPORT (ArmSetTTBR0)\r
-GCC_ASM_EXPORT (ArmGetTCR)\r
-GCC_ASM_EXPORT (ArmSetTCR)\r
-GCC_ASM_EXPORT (ArmGetMAIR)\r
-GCC_ASM_EXPORT (ArmSetMAIR)\r
-GCC_ASM_EXPORT (ArmWriteCpacr)\r
-GCC_ASM_EXPORT (ArmWriteAuxCr)\r
-GCC_ASM_EXPORT (ArmReadAuxCr)\r
-GCC_ASM_EXPORT (ArmInvalidateTlb)\r
-GCC_ASM_EXPORT (ArmUpdateTranslationTableEntry)\r
-GCC_ASM_EXPORT (ArmWriteCptr)\r
-GCC_ASM_EXPORT (ArmWriteScr)\r
-GCC_ASM_EXPORT (ArmWriteMVBar)\r
-GCC_ASM_EXPORT (ArmCallWFE)\r
-GCC_ASM_EXPORT (ArmCallSEV)\r
-GCC_ASM_EXPORT (ArmReadCpuActlr)\r
-GCC_ASM_EXPORT (ArmWriteCpuActlr)\r
-GCC_ASM_EXPORT (ArmReadSctlr)\r
-\r
-#------------------------------------------------------------------------------\r
-\r
 .set DAIF_RD_FIQ_BIT,   (1 << 6)\r
 .set DAIF_RD_IRQ_BIT,   (1 << 7)\r
 \r
-ASM_PFX(ArmReadMidr):\r
+ASM_FUNC(ArmReadMidr)\r
   mrs     x0, midr_el1        // Read from Main ID Register (MIDR)\r
   ret\r
 \r
-ASM_PFX(ArmCacheInfo):\r
+ASM_FUNC(ArmCacheInfo)\r
   mrs     x0, ctr_el0         // Read from Cache Type Regiter (CTR)\r
   ret\r
 \r
-ASM_PFX(ArmGetInterruptState):\r
+ASM_FUNC(ArmGetInterruptState)\r
   mrs     x0, daif\r
   tst     w0, #DAIF_RD_IRQ_BIT  // Check if IRQ is enabled. Enabled if 0 (Z=1)\r
   cset    w0, eq                // if Z=1 return 1, else 0\r
   ret\r
 \r
-ASM_PFX(ArmGetFiqState):\r
+ASM_FUNC(ArmGetFiqState)\r
   mrs     x0, daif\r
   tst     w0, #DAIF_RD_FIQ_BIT  // Check if FIQ is enabled. Enabled if 0 (Z=1)\r
   cset    w0, eq                // if Z=1 return 1, else 0\r
   ret\r
 \r
-ASM_PFX(ArmWriteCpacr):\r
+ASM_FUNC(ArmWriteCpacr)\r
   msr     cpacr_el1, x0      // Coprocessor Access Control Reg (CPACR)\r
   ret\r
 \r
-ASM_PFX(ArmWriteAuxCr):\r
+ASM_FUNC(ArmWriteAuxCr)\r
   EL1_OR_EL2(x1)\r
 1:msr     actlr_el1, x0      // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r
   ret\r
 2:msr     actlr_el2, x0      // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r
   ret\r
 \r
-ASM_PFX(ArmReadAuxCr):\r
+ASM_FUNC(ArmReadAuxCr)\r
   EL1_OR_EL2(x1)\r
 1:mrs     x0, actlr_el1      // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r
   ret\r
 2:mrs     x0, actlr_el2      // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r
   ret\r
 \r
-ASM_PFX(ArmSetTTBR0):\r
+ASM_FUNC(ArmSetTTBR0)\r
   EL1_OR_EL2_OR_EL3(x1)\r
 1:msr     ttbr0_el1, x0      // Translation Table Base Reg 0 (TTBR0)\r
   b       4f\r
@@ -94,17 +67,16 @@ ASM_PFX(ArmSetTTBR0):
 4:isb\r
   ret\r
 \r
-ASM_PFX(ArmGetTTBR0BaseAddress):\r
+ASM_FUNC(ArmGetTTBR0BaseAddress)\r
   EL1_OR_EL2(x1)\r
 1:mrs     x0, ttbr0_el1\r
   b       3f\r
 2:mrs     x0, ttbr0_el2\r
-3:LoadConstantToReg(0xFFFFFFFFFFFF, x1) /* Look at bottom 48 bits */\r
-  and     x0, x0, x1\r
+3:and     x0, x0, 0xFFFFFFFFFFFF  /* Look at bottom 48 bits */\r
   isb\r
   ret\r
 \r
-ASM_PFX(ArmGetTCR):\r
+ASM_FUNC(ArmGetTCR)\r
   EL1_OR_EL2_OR_EL3(x1)\r
 1:mrs     x0, tcr_el1\r
   b       4f\r
@@ -114,7 +86,7 @@ ASM_PFX(ArmGetTCR):
 4:isb\r
   ret\r
 \r
-ASM_PFX(ArmSetTCR):\r
+ASM_FUNC(ArmSetTCR)\r
   EL1_OR_EL2_OR_EL3(x1)\r
 1:msr     tcr_el1, x0\r
   b       4f\r
@@ -124,7 +96,7 @@ ASM_PFX(ArmSetTCR):
 4:isb\r
   ret\r
 \r
-ASM_PFX(ArmGetMAIR):\r
+ASM_FUNC(ArmGetMAIR)\r
   EL1_OR_EL2_OR_EL3(x1)\r
 1:mrs     x0, mair_el1\r
   b       4f\r
@@ -134,7 +106,7 @@ ASM_PFX(ArmGetMAIR):
 4:isb\r
   ret\r
 \r
-ASM_PFX(ArmSetMAIR):\r
+ASM_FUNC(ArmSetMAIR)\r
   EL1_OR_EL2_OR_EL3(x1)\r
 1:msr     mair_el1, x0\r
   b       4f\r
@@ -151,7 +123,7 @@ ASM_PFX(ArmSetMAIR):
 //  IN VOID  *TranslationTableEntry  // X0\r
 //  IN VOID  *MVA                    // X1\r
 //  );\r
-ASM_PFX(ArmUpdateTranslationTableEntry):\r
+ASM_FUNC(ArmUpdateTranslationTableEntry)\r
    dc      civac, x0             // Clean and invalidate data line\r
    dsb     sy\r
    EL1_OR_EL2_OR_EL3(x0)\r
@@ -164,7 +136,7 @@ ASM_PFX(ArmUpdateTranslationTableEntry):
    isb\r
    ret\r
 \r
-ASM_PFX(ArmInvalidateTlb):\r
+ASM_FUNC(ArmInvalidateTlb)\r
    EL1_OR_EL2_OR_EL3(x0)\r
 1: tlbi  vmalle1\r
    b     4f\r
@@ -175,38 +147,38 @@ ASM_PFX(ArmInvalidateTlb):
    isb\r
    ret\r
 \r
-ASM_PFX(ArmWriteCptr):\r
+ASM_FUNC(ArmWriteCptr)\r
   msr     cptr_el3, x0           // EL3 Coprocessor Trap Reg (CPTR)\r
   ret\r
 \r
-ASM_PFX(ArmWriteScr):\r
+ASM_FUNC(ArmWriteScr)\r
   msr     scr_el3, x0            // Secure configuration register EL3\r
   isb\r
   ret\r
 \r
-ASM_PFX(ArmWriteMVBar):\r
+ASM_FUNC(ArmWriteMVBar)\r
   msr    vbar_el3, x0            // Exception Vector Base address for Monitor on EL3\r
   ret\r
 \r
-ASM_PFX(ArmCallWFE):\r
+ASM_FUNC(ArmCallWFE)\r
   wfe\r
   ret\r
 \r
-ASM_PFX(ArmCallSEV):\r
+ASM_FUNC(ArmCallSEV)\r
   sev\r
   ret\r
 \r
-ASM_PFX(ArmReadCpuActlr):\r
+ASM_FUNC(ArmReadCpuActlr)\r
   mrs   x0, S3_1_c15_c2_0\r
   ret\r
 \r
-ASM_PFX(ArmWriteCpuActlr):\r
+ASM_FUNC(ArmWriteCpuActlr)\r
   msr   S3_1_c15_c2_0, x0\r
   dsb   sy\r
   isb\r
   ret\r
 \r
-ASM_PFX(ArmReadSctlr):\r
+ASM_FUNC(ArmReadSctlr)\r
   EL1_OR_EL2_OR_EL3(x1)\r
 1:mrs   x0, sctlr_el1\r
   ret\r