ArmPkg/ArmLib: switch to ASM_FUNC() asm macro

[mirror_edk2.git] / ArmPkg / Library / ArmLib / Common / Arm / ArmLibSupport.S

diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
index 5d1194e7e219ea6dec4b69191383ca693dc1c635..a0b5ed500298f9ccfdde3882040647ad212f36cb 100644 (file)
--- a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
+++ b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
@@ -2,6 +2,7 @@
 #\r
 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
 # Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.\r
+# Copyright (c) 2016, Linaro Limited. All rights reserved.\r
 #\r
 # This program and the accompanying materials\r
 # are licensed and made available under the terms and conditions of the BSD License\r
@@ -15,65 +16,33 @@
 \r
 #include <AsmMacroIoLib.h>\r
 \r
-.text\r
-.align 2\r
-GCC_ASM_EXPORT(ArmReadMidr)\r
-GCC_ASM_EXPORT(ArmCacheInfo)\r
-GCC_ASM_EXPORT(ArmGetInterruptState)\r
-GCC_ASM_EXPORT(ArmGetFiqState)\r
-GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)\r
-GCC_ASM_EXPORT(ArmSetTTBR0)\r
-GCC_ASM_EXPORT(ArmSetTTBCR)\r
-GCC_ASM_EXPORT(ArmSetDomainAccessControl)\r
-GCC_ASM_EXPORT(CPSRMaskInsert)\r
-GCC_ASM_EXPORT(CPSRRead)\r
-GCC_ASM_EXPORT(ArmReadCpacr)\r
-GCC_ASM_EXPORT(ArmWriteCpacr)\r
-GCC_ASM_EXPORT(ArmWriteAuxCr)\r
-GCC_ASM_EXPORT(ArmReadAuxCr)\r
-GCC_ASM_EXPORT(ArmInvalidateTlb)\r
-GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)\r
-GCC_ASM_EXPORT(ArmReadScr)\r
-GCC_ASM_EXPORT(ArmWriteScr)\r
-GCC_ASM_EXPORT(ArmReadMVBar)\r
-GCC_ASM_EXPORT(ArmWriteMVBar)\r
-GCC_ASM_EXPORT(ArmReadHVBar)\r
-GCC_ASM_EXPORT(ArmWriteHVBar)\r
-GCC_ASM_EXPORT(ArmCallWFE)\r
-GCC_ASM_EXPORT(ArmCallSEV)\r
-GCC_ASM_EXPORT(ArmReadSctlr)\r
-GCC_ASM_EXPORT(ArmReadCpuActlr)\r
-GCC_ASM_EXPORT(ArmWriteCpuActlr)\r
-\r
-#------------------------------------------------------------------------------\r
-\r
-ASM_PFX(ArmReadMidr):\r
+ASM_FUNC(ArmReadMidr)\r
   mrc     p15,0,R0,c0,c0,0\r
   bx      LR\r
 \r
-ASM_PFX(ArmCacheInfo):\r
+ASM_FUNC(ArmCacheInfo)\r
   mrc     p15,0,R0,c0,c0,1\r
   bx      LR\r
 \r
-ASM_PFX(ArmGetInterruptState):\r
+ASM_FUNC(ArmGetInterruptState)\r
   mrs     R0,CPSR\r
   tst     R0,#0x80      @Check if IRQ is enabled.\r
   moveq   R0,#1\r
   movne   R0,#0\r
   bx      LR\r
 \r
-ASM_PFX(ArmGetFiqState):\r
+ASM_FUNC(ArmGetFiqState)\r
   mrs     R0,CPSR\r
   tst     R0,#0x40      @Check if FIQ is enabled.\r
   moveq   R0,#1\r
   movne   R0,#0\r
   bx      LR\r
 \r
-ASM_PFX(ArmSetDomainAccessControl):\r
+ASM_FUNC(ArmSetDomainAccessControl)\r
   mcr     p15,0,r0,c3,c0,0\r
   bx      lr\r
 \r
-ASM_PFX(CPSRMaskInsert):    @ on entry, r0 is the mask and r1 is the field to insert\r
+ASM_FUNC(CPSRMaskInsert)    @ on entry, r0 is the mask and r1 is the field to insert\r
   stmfd   sp!, {r4-r12, lr} @ save all the banked registers\r
   mov     r3, sp            @ copy the stack pointer into a non-banked register\r
   mrs     r2, cpsr          @ read the cpsr\r
@@ -86,40 +55,40 @@ ASM_PFX(CPSRMaskInsert):    @ on entry, r0 is the mask and r1 is the field to in
   ldmfd   sp!, {r4-r12, lr} @ restore registers\r
   bx      lr                @ return (hopefully thumb-safe!)\r
 \r
-ASM_PFX(CPSRRead):\r
+ASM_FUNC(CPSRRead)\r
   mrs     r0, cpsr\r
   bx      lr\r
 \r
-ASM_PFX(ArmReadCpacr):\r
+ASM_FUNC(ArmReadCpacr)\r
   mrc     p15, 0, r0, c1, c0, 2\r
   bx      lr\r
 \r
-ASM_PFX(ArmWriteCpacr):\r
+ASM_FUNC(ArmWriteCpacr)\r
   mcr     p15, 0, r0, c1, c0, 2\r
   isb\r
   bx      lr\r
 \r
-ASM_PFX(ArmWriteAuxCr):\r
+ASM_FUNC(ArmWriteAuxCr)\r
   mcr     p15, 0, r0, c1, c0, 1\r
   bx      lr\r
 \r
-ASM_PFX(ArmReadAuxCr):\r
+ASM_FUNC(ArmReadAuxCr)\r
   mrc     p15, 0, r0, c1, c0, 1\r
   bx      lr\r
 \r
-ASM_PFX(ArmSetTTBR0):\r
+ASM_FUNC(ArmSetTTBR0)\r
   mcr     p15,0,r0,c2,c0,0\r
   isb\r
   bx      lr\r
 \r
-ASM_PFX(ArmSetTTBCR):\r
+ASM_FUNC(ArmSetTTBCR)\r
   mcr     p15, 0, r0, c2, c0, 2\r
   isb\r
   bx      lr\r
 \r
-ASM_PFX(ArmGetTTBR0BaseAddress):\r
+ASM_FUNC(ArmGetTTBR0BaseAddress)\r
   mrc     p15,0,r0,c2,c0,0\r
-  LoadConstantToReg(0xFFFFC000, r1)\r
+  MOV32   (r1, 0xFFFFC000)\r
   and     r0, r0, r1\r
   isb\r
   bx      lr\r
@@ -130,7 +99,7 @@ ASM_PFX(ArmGetTTBR0BaseAddress):
 //  IN VOID  *TranslationTableEntry  // R0\r
 //  IN VOID  *MVA                    // R1\r
 //  );\r
-ASM_PFX(ArmUpdateTranslationTableEntry):\r
+ASM_FUNC(ArmUpdateTranslationTableEntry)\r
   mcr     p15,0,R0,c7,c14,1     @ DCCIMVAC Clean data cache by MVA\r
   dsb\r
   mcr     p15,0,R1,c8,c7,1      @ TLBIMVA TLB Invalidate MVA\r
@@ -139,7 +108,7 @@ ASM_PFX(ArmUpdateTranslationTableEntry):
   isb\r
   bx      lr\r
 \r
-ASM_PFX(ArmInvalidateTlb):\r
+ASM_FUNC(ArmInvalidateTlb)\r
   mov     r0,#0\r
   mcr     p15,0,r0,c8,c7,0\r
   mcr     p15,0,R9,c7,c5,6      @ BPIALL Invalidate Branch predictor array. R9 == NoOp\r
@@ -147,48 +116,48 @@ ASM_PFX(ArmInvalidateTlb):
   isb\r
   bx      lr\r
 \r
-ASM_PFX(ArmReadScr):\r
+ASM_FUNC(ArmReadScr)\r
   mrc     p15, 0, r0, c1, c1, 0\r
   bx      lr\r
 \r
-ASM_PFX(ArmWriteScr):\r
+ASM_FUNC(ArmWriteScr)\r
   mcr     p15, 0, r0, c1, c1, 0\r
   isb\r
   bx      lr\r
 \r
-ASM_PFX(ArmReadHVBar):\r
+ASM_FUNC(ArmReadHVBar)\r
   mrc     p15, 4, r0, c12, c0, 0\r
   bx      lr\r
 \r
-ASM_PFX(ArmWriteHVBar):\r
+ASM_FUNC(ArmWriteHVBar)\r
   mcr     p15, 4, r0, c12, c0, 0\r
   bx      lr\r
 \r
-ASM_PFX(ArmReadMVBar):\r
+ASM_FUNC(ArmReadMVBar)\r
   mrc     p15, 0, r0, c12, c0, 1\r
   bx      lr\r
 \r
-ASM_PFX(ArmWriteMVBar):\r
+ASM_FUNC(ArmWriteMVBar)\r
   mcr     p15, 0, r0, c12, c0, 1\r
   bx      lr\r
 \r
-ASM_PFX(ArmCallWFE):\r
+ASM_FUNC(ArmCallWFE)\r
   wfe\r
   bx      lr\r
 \r
-ASM_PFX(ArmCallSEV):\r
+ASM_FUNC(ArmCallSEV)\r
   sev\r
   bx      lr\r
 \r
-ASM_PFX(ArmReadSctlr):\r
+ASM_FUNC(ArmReadSctlr)\r
   mrc     p15, 0, r0, c1, c0, 0      @ Read SCTLR into R0 (Read control register configuration data)\r
   bx      lr\r
 \r
-ASM_PFX(ArmReadCpuActlr):\r
+ASM_FUNC(ArmReadCpuActlr)\r
   mrc     p15, 0, r0, c1, c0, 1\r
   bx      lr\r
 \r
-ASM_PFX(ArmWriteCpuActlr):\r
+ASM_FUNC(ArmWriteCpuActlr)\r
   mcr     p15, 0, r0, c1, c0, 1\r
   dsb\r
   isb\r