ArmPkg/ArmBaseLib: clean up directory structure

[mirror_edk2.git] / ArmPkg / Library / ArmLib / Common / Arm / ArmLibSupport.asm

diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
deleted file mode 100644 (file)
index 85b0fee..0000000
--- a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
+++ /dev/null
@@ -1,169 +0,0 @@
-//------------------------------------------------------------------------------\r
-//\r
-// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-// Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution.  The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//------------------------------------------------------------------------------\r
-\r
-    INCLUDE AsmMacroIoLib.inc\r
-\r
-\r
-    INCLUDE AsmMacroExport.inc\r
-\r
- RVCT_ASM_EXPORT ArmReadMidr\r
-  mrc     p15,0,R0,c0,c0,0\r
-  bx      LR\r
-\r
- RVCT_ASM_EXPORT ArmCacheInfo\r
-  mrc     p15,0,R0,c0,c0,1\r
-  bx      LR\r
-\r
- RVCT_ASM_EXPORT ArmGetInterruptState\r
-  mrs     R0,CPSR\r
-  tst     R0,#0x80      // Check if IRQ is enabled.\r
-  moveq   R0,#1\r
-  movne   R0,#0\r
-  bx      LR\r
-\r
- RVCT_ASM_EXPORT ArmGetFiqState\r
-  mrs     R0,CPSR\r
-  tst     R0,#0x40      // Check if FIQ is enabled.\r
-  moveq   R0,#1\r
-  movne   R0,#0\r
-  bx      LR\r
-\r
- RVCT_ASM_EXPORT ArmSetDomainAccessControl\r
-  mcr     p15,0,r0,c3,c0,0\r
-  bx      lr\r
-\r
- RVCT_ASM_EXPORT CPSRMaskInsert\r
-  stmfd   sp!, {r4-r12, lr} // save all the banked registers\r
-  mov     r3, sp            // copy the stack pointer into a non-banked register\r
-  mrs     r2, cpsr          // read the cpsr\r
-  bic     r2, r2, r0        // clear mask in the cpsr\r
-  and     r1, r1, r0        // clear bits outside the mask in the input\r
-  orr     r2, r2, r1        // set field\r
-  msr     cpsr_cxsf, r2     // write back cpsr (may have caused a mode switch)\r
-  isb\r
-  mov     sp, r3            // restore stack pointer\r
-  ldmfd   sp!, {r4-r12, lr} // restore registers\r
-  bx      lr                // return (hopefully thumb-safe!)             // return (hopefully thumb-safe!)\r
-\r
- RVCT_ASM_EXPORT CPSRRead\r
-  mrs     r0, cpsr\r
-  bx      lr\r
-\r
- RVCT_ASM_EXPORT ArmReadCpacr\r
-  mrc     p15, 0, r0, c1, c0, 2\r
-  bx      lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteCpacr\r
-  mcr     p15, 0, r0, c1, c0, 2\r
-  isb\r
-  bx      lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteAuxCr\r
-  mcr     p15, 0, r0, c1, c0, 1\r
-  bx      lr\r
-\r
- RVCT_ASM_EXPORT ArmReadAuxCr\r
-  mrc     p15, 0, r0, c1, c0, 1\r
-  bx      lr\r
-\r
- RVCT_ASM_EXPORT ArmSetTTBR0\r
-  mcr     p15,0,r0,c2,c0,0\r
-  isb\r
-  bx      lr\r
-\r
- RVCT_ASM_EXPORT ArmSetTTBCR\r
-  mcr     p15, 0, r0, c2, c0, 2\r
-  isb\r
-  bx      lr\r
-\r
- RVCT_ASM_EXPORT ArmGetTTBR0BaseAddress\r
-  mrc     p15,0,r0,c2,c0,0\r
-  MOV32   r1, 0xFFFFC000\r
-  and     r0, r0, r1\r
-  isb\r
-  bx      lr\r
-\r
-//\r
-//VOID\r
-//ArmUpdateTranslationTableEntry (\r
-//  IN VOID  *TranslationTableEntry  // R0\r
-//  IN VOID  *MVA                    // R1\r
-//  );\r
- RVCT_ASM_EXPORT ArmUpdateTranslationTableEntry\r
-  mcr     p15,0,R0,c7,c14,1     // DCCIMVAC Clean data cache by MVA\r
-  dsb\r
-  mcr     p15,0,R1,c8,c7,1      // TLBIMVA TLB Invalidate MVA\r
-  mcr     p15,0,R9,c7,c5,6      // BPIALL Invalidate Branch predictor array. R9 == NoOp\r
-  dsb\r
-  isb\r
-  bx      lr\r
-\r
- RVCT_ASM_EXPORT ArmInvalidateTlb\r
-  mov     r0,#0\r
-  mcr     p15,0,r0,c8,c7,0\r
-  mcr     p15,0,R9,c7,c5,6      // BPIALL Invalidate Branch predictor array. R9 == NoOp\r
-  dsb\r
-  isb\r
-  bx      lr\r
-\r
- RVCT_ASM_EXPORT ArmReadScr\r
-  mrc     p15, 0, r0, c1, c1, 0\r
-  bx      lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteScr\r
-  mcr     p15, 0, r0, c1, c1, 0\r
-  isb\r
-  bx      lr\r
-\r
- RVCT_ASM_EXPORT ArmReadHVBar\r
-  mrc     p15, 4, r0, c12, c0, 0\r
-  bx      lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteHVBar\r
-  mcr     p15, 4, r0, c12, c0, 0\r
-  bx      lr\r
-\r
- RVCT_ASM_EXPORT ArmReadMVBar\r
-  mrc     p15, 0, r0, c12, c0, 1\r
-  bx      lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteMVBar\r
-  mcr     p15, 0, r0, c12, c0, 1\r
-  bx      lr\r
-\r
- RVCT_ASM_EXPORT ArmCallWFE\r
-  wfe\r
-  bx      lr\r
-\r
- RVCT_ASM_EXPORT ArmCallSEV\r
-  sev\r
-  bx      lr\r
-\r
- RVCT_ASM_EXPORT ArmReadSctlr\r
-  mrc     p15, 0, r0, c1, c0, 0      // Read SCTLR into R0 (Read control register configuration data)\r
-  bx      lr\r
-\r
-\r
- RVCT_ASM_EXPORT ArmReadCpuActlr\r
-  mrc     p15, 0, r0, c1, c0, 1\r
-  bx      lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteCpuActlr\r
-  mcr     p15, 0, r0, c1, c0, 1\r
-  dsb\r
-  isb\r
-  bx      lr\r
-\r
-  END\r