Fixes to get CodeSourcery GCC and RVCT 3.1 compiling.

[mirror_edk2.git] / ArmPkg / Library / ArmLib / Common / ArmLibSupport.asm

diff --git a/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm
index 0b023fed42826ea824ee545014dbe02beb5e4da4..850bb9691cbdf31f60117adc4b8e4d9a656122dc 100644 (file)
--- a/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm
+++ b/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm
@@ -12,6 +12,9 @@
 //
 //------------------------------------------------------------------------------
 
+#include <AsmMacroIoLib.h>
+    
+    INCLUDE AsmMacroIoLib.inc
 
     EXPORT  Cp15IdCode
     EXPORT  Cp15CacheInfo
@@ -41,55 +44,55 @@ Cp15CacheInfo
 
 ArmIsMPCore
   mrc     p15,0,R0,c0,c0,5
-  # Get Multiprocessing extension (bit31) & U bit (bit30)
+  // Get Multiprocessing extension (bit31) & U bit (bit30)
   and     R0, R0, #0xC0000000
-  # if bit30 == 0 then the processor is part of a multiprocessor system)
+  // if bit30 == 0 then the processor is part of a multiprocessor system)
   and     R0, R0, #0x80000000
   bx      LR
 
 ArmEnableInterrupts
-\s\smrs     R0,CPSR
-\s\sbic     R0,R0,#0x80\s\s\s\s;Enable IRQ interrupts
-\s\smsr     CPSR_c,R0
-\s\sbx      LR
+  mrs     R0,CPSR
+  bic     R0,R0,#0x80    ;Enable IRQ interrupts
+  msr     CPSR_c,R0
+  bx      LR
 
 ArmDisableInterrupts
-\s\smrs     R0,CPSR
-\s\sorr     R1,R0,#0x80\s\s\s\s;Disable IRQ interrupts
-\s\smsr     CPSR_c,R1
+  mrs     R0,CPSR
+  orr     R1,R0,#0x80    ;Disable IRQ interrupts
+  msr     CPSR_c,R1
   tst     R0,#0x80
   moveq   R0,#1
   movne   R0,#0
-\s\sbx      LR
+  bx      LR
 
 ArmGetInterruptState
-\s\smrs     R0,CPSR
-\s\stst     R0,#0x80\s\s    ;Check if IRQ is enabled.
-\s\smoveq   R0,#1
-\s\smovne   R0,#0
-\s\sbx      LR
+  mrs     R0,CPSR
+  tst     R0,#0x80      ;Check if IRQ is enabled.
+  moveq   R0,#1
+  movne   R0,#0
+  bx      LR
 
 ArmEnableFiq
-\s\smrs     R0,CPSR
-\s\sbic     R0,R0,#0x40\s\s\s\s;Enable IRQ interrupts
-\s\smsr     CPSR_c,R0
-\s\sbx      LR
+  mrs     R0,CPSR
+  bic     R0,R0,#0x40    ;Enable IRQ interrupts
+  msr     CPSR_c,R0
+  bx      LR
 
 ArmDisableFiq
-\s\smrs     R0,CPSR
-\s\sorr     R1,R0,#0x40\s\s\s\s;Disable IRQ interrupts
-\s\smsr     CPSR_c,R1
+  mrs     R0,CPSR
+  orr     R1,R0,#0x40    ;Disable IRQ interrupts
+  msr     CPSR_c,R1
   tst     R0,#0x40
   moveq   R0,#1
   movne   R0,#0
-\s\sbx      LR
+  bx      LR
 
 ArmGetFiqState
-\s\smrs     R0,CPSR
-\s\stst     R0,#0x40\s\s    ;Check if IRQ is enabled.
-\s\smoveq   R0,#1
-\s\smovne   R0,#0
-\s\sbx      LR
+  mrs     R0,CPSR
+  tst     R0,#0x40      ;Check if IRQ is enabled.
+  moveq   R0,#1
+  movne   R0,#0
+  bx      LR
   
 ArmInvalidateTlb
   mov     r0,#0
@@ -102,7 +105,8 @@ ArmSetTTBR0
 
 ArmGetTTBR0BaseAddress
   mrc     p15,0,r0,c2,c0,0
-  and     r0, r0, #0xFFFFC000
+  LoadConstantToReg(0xFFFFC000,r1)  // and     r0, r0, #0xFFFFC000
+  and     r0, r0, r1
   bx      lr
 
 ArmSetDomainAccessControl