ArmPkg/ArmMmuLib: support page tables in cacheable memory only

[mirror_edk2.git] / ArmPkg / Library / ArmMmuLib / AArch64 / ArmMmuLibCore.c

diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
index 1fb3bbec6347852bdf2e3c5d392e6e98f77dc463..c78297084207366b32c135563000c36884f5c04b 100644 (file)
--- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
+++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
@@ -627,6 +627,19 @@ ArmConfigureMmu (
     return RETURN_UNSUPPORTED;\r
   }\r
 \r
+  //\r
+  // Translation table walks are always cache coherent on ARMv8-A, so cache\r
+  // maintenance on page tables is never needed. Since there is a risk of\r
+  // loss of coherency when using mismatched attributes, and given that memory\r
+  // is mapped cacheable except for extraordinary cases (such as non-coherent\r
+  // DMA), have the page table walker perform cached accesses as well, and\r
+  // assert below that that matches the attributes we use for CPU accesses to\r
+  // the region.\r
+  //\r
+  TCR |= TCR_SH_INNER_SHAREABLE |\r
+         TCR_RGN_OUTER_WRITE_BACK_ALLOC |\r
+         TCR_RGN_INNER_WRITE_BACK_ALLOC;\r
+\r
   // Set TCR\r
   ArmSetTCR (TCR);\r
 \r
@@ -672,11 +685,15 @@ ArmConfigureMmu (
 \r
   TranslationTableAttribute = TT_ATTR_INDX_INVALID;\r
   while (MemoryTable->Length != 0) {\r
-    // Find the memory attribute for the Translation Table\r
-    if (((UINTN)TranslationTable >= MemoryTable->PhysicalBase) &&\r
-        ((UINTN)TranslationTable <= MemoryTable->PhysicalBase - 1 + MemoryTable->Length)) {\r
-      TranslationTableAttribute = MemoryTable->Attributes;\r
-    }\r
+\r
+    DEBUG_CODE_BEGIN ();\r
+      // Find the memory attribute for the Translation Table\r
+      if ((UINTN)TranslationTable >= MemoryTable->PhysicalBase &&\r
+          (UINTN)TranslationTable + RootTableEntrySize <= MemoryTable->PhysicalBase +\r
+                                                          MemoryTable->Length) {\r
+        TranslationTableAttribute = MemoryTable->Attributes;\r
+      }\r
+    DEBUG_CODE_END ();\r
 \r
     Status = FillTranslationTable (TranslationTable, MemoryTable);\r
     if (RETURN_ERROR (Status)) {\r
@@ -685,26 +702,8 @@ ArmConfigureMmu (
     MemoryTable++;\r
   }\r
 \r
-  // Translate the Memory Attributes into Translation Table Register Attributes\r
-  if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) ||\r
-      (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED)) {\r
-    TCR |= TCR_SH_NON_SHAREABLE | TCR_RGN_OUTER_NON_CACHEABLE | TCR_RGN_INNER_NON_CACHEABLE;\r
-  } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||\r
-      (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) {\r
-    TCR |= TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WRITE_BACK_ALLOC | TCR_RGN_INNER_WRITE_BACK_ALLOC;\r
-  } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) ||\r
-      (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH)) {\r
-    TCR |= TCR_SH_NON_SHAREABLE | TCR_RGN_OUTER_WRITE_THROUGH | TCR_RGN_INNER_WRITE_THROUGH;\r
-  } else {\r
-    // If we failed to find a mapping that contains the root translation table then it probably means the translation table\r
-    // is not mapped in the given memory map.\r
-    ASSERT (0);\r
-    Status = RETURN_UNSUPPORTED;\r
-    goto FREE_TRANSLATION_TABLE;\r
-  }\r
-\r
-  // Set again TCR after getting the Translation Table attributes\r
-  ArmSetTCR (TCR);\r
+  ASSERT (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK ||\r
+          TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK);\r
 \r
   ArmSetMAIR (MAIR_ATTR(TT_ATTR_INDX_DEVICE_MEMORY, MAIR_ATTR_DEVICE_MEMORY) |                      // mapped to EFI_MEMORY_UC\r
               MAIR_ATTR(TT_ATTR_INDX_MEMORY_NON_CACHEABLE, MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE) | // mapped to EFI_MEMORY_WC\r