)\r
{\r
switch (Attributes) {\r
+ case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:\r
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:\r
+ return TT_ATTR_INDX_MEMORY_WRITE_BACK;\r
+\r
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:\r
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:\r
return TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;\r
}\r
\r
STATIC\r
-RETURN_STATUS\r
+EFI_STATUS\r
UpdateRegionMapping (\r
IN UINT64 *RootTable,\r
IN UINT64 RegionStart,\r
// Ensure the Length is aligned on 4KB boundary\r
if ((RegionLength == 0) || ((RegionLength & (SIZE_4KB - 1)) != 0)) {\r
ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);\r
- return RETURN_INVALID_PARAMETER;\r
+ return EFI_INVALID_PARAMETER;\r
}\r
\r
do {\r
BlockEntry = GetBlockEntryListFromAddress (RootTable, RegionStart, &TableLevel, &BlockEntrySize, &LastBlockEntry);\r
if (BlockEntry == NULL) {\r
// GetBlockEntryListFromAddress() return NULL when it fails to allocate new pages from the Translation Tables\r
- return RETURN_OUT_OF_RESOURCES;\r
+ return EFI_OUT_OF_RESOURCES;\r
}\r
\r
if (TableLevel != 3) {\r
\r
// Break the inner loop when next block is a table\r
// Rerun GetBlockEntryListFromAddress to avoid page table memory leak\r
- if (TableLevel != 3 &&\r
+ if (TableLevel != 3 && BlockEntry <= LastBlockEntry &&\r
(*BlockEntry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY) {\r
break;\r
}\r
} while ((RegionLength >= BlockEntrySize) && (BlockEntry <= LastBlockEntry));\r
} while (RegionLength != 0);\r
\r
- return RETURN_SUCCESS;\r
+ return EFI_SUCCESS;\r
}\r
\r
STATIC\r
-RETURN_STATUS\r
+EFI_STATUS\r
FillTranslationTable (\r
IN UINT64 *RootTable,\r
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion\r
return PageAttributes | TT_AF;\r
}\r
\r
-RETURN_STATUS\r
-SetMemoryAttributes (\r
+EFI_STATUS\r
+ArmSetMemoryAttributes (\r
IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
IN UINT64 Length,\r
- IN UINT64 Attributes,\r
- IN EFI_PHYSICAL_ADDRESS VirtualMask\r
+ IN UINT64 Attributes\r
)\r
{\r
- RETURN_STATUS Status;\r
+ EFI_STATUS Status;\r
UINT64 *TranslationTable;\r
UINT64 PageAttributes;\r
UINT64 PageAttributeMask;\r
Length,\r
PageAttributes,\r
PageAttributeMask);\r
- if (RETURN_ERROR (Status)) {\r
+ if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
// Invalidate all TLB entries so changes are synced\r
ArmInvalidateTlb ();\r
\r
- return RETURN_SUCCESS;\r
+ return EFI_SUCCESS;\r
}\r
\r
STATIC\r
-RETURN_STATUS\r
+EFI_STATUS\r
SetMemoryRegionAttribute (\r
IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
IN UINT64 Length,\r
IN UINT64 BlockEntryMask\r
)\r
{\r
- RETURN_STATUS Status;\r
+ EFI_STATUS Status;\r
UINT64 *RootTable;\r
\r
RootTable = ArmGetTTBR0BaseAddress ();\r
\r
Status = UpdateRegionMapping (RootTable, BaseAddress, Length, Attributes, BlockEntryMask);\r
- if (RETURN_ERROR (Status)) {\r
+ if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
// Invalidate all TLB entries so changes are synced\r
ArmInvalidateTlb ();\r
\r
- return RETURN_SUCCESS;\r
+ return EFI_SUCCESS;\r
}\r
\r
-RETURN_STATUS\r
+EFI_STATUS\r
ArmSetMemoryRegionNoExec (\r
IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
IN UINT64 Length\r
~TT_ADDRESS_MASK_BLOCK_ENTRY);\r
}\r
\r
-RETURN_STATUS\r
+EFI_STATUS\r
ArmClearMemoryRegionNoExec (\r
IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
IN UINT64 Length\r
Mask);\r
}\r
\r
-RETURN_STATUS\r
+EFI_STATUS\r
ArmSetMemoryRegionReadOnly (\r
IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
IN UINT64 Length\r
~TT_ADDRESS_MASK_BLOCK_ENTRY);\r
}\r
\r
-RETURN_STATUS\r
+EFI_STATUS\r
ArmClearMemoryRegionReadOnly (\r
IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
IN UINT64 Length\r
~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK));\r
}\r
\r
-RETURN_STATUS\r
+EFI_STATUS\r
EFIAPI\r
ArmConfigureMmu (\r
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,\r
UINTN T0SZ;\r
UINTN RootTableEntryCount;\r
UINT64 TCR;\r
- RETURN_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
if(MemoryTable == NULL) {\r
ASSERT (MemoryTable != NULL);\r
- return RETURN_INVALID_PARAMETER;\r
+ return EFI_INVALID_PARAMETER;\r
}\r
\r
- // Cover the entire GCD memory space\r
- MaxAddress = (1UL << PcdGet8 (PcdPrePiCpuMemorySize)) - 1;\r
+ //\r
+ // Limit the virtual address space to what we can actually use: UEFI\r
+ // mandates a 1:1 mapping, so no point in making the virtual address\r
+ // space larger than the physical address space. We also have to take\r
+ // into account the architectural limitations that result from UEFI's\r
+ // use of 4 KB pages.\r
+ //\r
+ MaxAddress = MIN (LShiftU64 (1ULL, ArmGetPhysicalAddressBits ()) - 1,\r
+ MAX_ALLOC_ADDRESS);\r
\r
// Lookup the Table Level to get the information\r
LookupAddresstoRootTable (MaxAddress, &T0SZ, &RootTableEntryCount);\r
} else {\r
DEBUG ((EFI_D_ERROR, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n", MaxAddress));\r
ASSERT (0); // Bigger than 48-bit memory space are not supported\r
- return RETURN_UNSUPPORTED;\r
+ return EFI_UNSUPPORTED;\r
}\r
} else if (ArmReadCurrentEL () == AARCH64_EL1) {\r
// Due to Cortex-A57 erratum #822227 we must set TG1[1] == 1, regardless of EPD1.\r
} else {\r
DEBUG ((EFI_D_ERROR, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n", MaxAddress));\r
ASSERT (0); // Bigger than 48-bit memory space are not supported\r
- return RETURN_UNSUPPORTED;\r
+ return EFI_UNSUPPORTED;\r
}\r
} else {\r
ASSERT (0); // UEFI is only expected to run at EL2 and EL1, not EL3.\r
- return RETURN_UNSUPPORTED;\r
+ return EFI_UNSUPPORTED;\r
}\r
\r
//\r
// Allocate pages for translation table\r
TranslationTable = AllocatePages (1);\r
if (TranslationTable == NULL) {\r
- return RETURN_OUT_OF_RESOURCES;\r
+ return EFI_OUT_OF_RESOURCES;\r
}\r
// We set TTBR0 just after allocating the table to retrieve its location from the subsequent\r
// functions without needing to pass this value across the functions. The MMU is only enabled\r
DEBUG_CODE_END ();\r
\r
Status = FillTranslationTable (TranslationTable, MemoryTable);\r
- if (RETURN_ERROR (Status)) {\r
+ if (EFI_ERROR (Status)) {\r
goto FREE_TRANSLATION_TABLE;\r
}\r
MemoryTable++;\r
MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_BACK, MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK)); // mapped to EFI_MEMORY_WB\r
\r
ArmDisableAlignmentCheck ();\r
+ ArmEnableStackAlignmentCheck ();\r
ArmEnableInstructionCache ();\r
ArmEnableDataCache ();\r
\r
ArmEnableMmu ();\r
- return RETURN_SUCCESS;\r
+ return EFI_SUCCESS;\r
\r
FREE_TRANSLATION_TABLE:\r
FreePages (TranslationTable, 1);\r
projects / mirror_edk2.git / blobdiff