#define ID_MMFR0_SHR_IMP_HW_COHERENT 1\r
#define ID_MMFR0_SHR_IGNORED 0xf\r
\r
+#define __EFI_MEMORY_RWX 0 // no restrictions\r
+\r
#define CACHE_ATTRIBUTE_MASK (EFI_MEMORY_UC | \\r
EFI_MEMORY_WC | \\r
EFI_MEMORY_WT | \\r
UINT32 SectionDescriptor;\r
UINT32 TranslationTable;\r
UINT32 BaseSectionAddress;\r
+ UINT32 FirstPageOffset;\r
\r
switch (Attributes) {\r
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:\r
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:\r
PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_BACK;\r
break;\r
+ case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:\r
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:\r
+ PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_BACK;\r
+ PageAttributes &= ~TT_DESCRIPTOR_PAGE_S_SHARED;\r
+ break;\r
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:\r
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:\r
PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_THROUGH;\r
TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;\r
}\r
\r
- PageEntry = ((UINT32 *)(TranslationTable) + ((PhysicalBase & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT));\r
+ FirstPageOffset = (PhysicalBase & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;\r
+ PageEntry = (UINT32 *)TranslationTable + FirstPageOffset;\r
Pages = RemainLength / TT_DESCRIPTOR_PAGE_SIZE;\r
\r
+ ASSERT (FirstPageOffset + Pages <= TRANSLATION_TABLE_PAGE_COUNT);\r
+\r
for (Index = 0; Index < Pages; Index++) {\r
*PageEntry++ = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(PhysicalBase) | PageAttributes;\r
PhysicalBase += TT_DESCRIPTOR_PAGE_SIZE;\r
UINT32 Attributes;\r
UINT32 PhysicalBase;\r
UINT64 RemainLength;\r
+ UINT32 PageMapLength;\r
\r
ASSERT(MemoryRegion->Length > 0);\r
\r
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:\r
Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);\r
break;\r
+ case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:\r
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);\r
+ Attributes &= ~TT_DESCRIPTOR_SECTION_S_SHARED;\r
+ break;\r
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:\r
Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);\r
break;\r
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:\r
Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);\r
break;\r
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:\r
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);\r
+ Attributes &= ~TT_DESCRIPTOR_SECTION_S_SHARED;\r
+ break;\r
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:\r
Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1);\r
break;\r
SectionEntry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);\r
\r
while (RemainLength != 0) {\r
- if (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE == 0) {\r
- if (RemainLength >= TT_DESCRIPTOR_SECTION_SIZE) {\r
- // Case: Physical address aligned on the Section Size (1MB) && the length is greater than the Section Size\r
- *SectionEntry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;\r
- PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;\r
- } else {\r
- // Case: Physical address aligned on the Section Size (1MB) && the length does not fill a section\r
- PopulateLevel2PageTable (SectionEntry++, PhysicalBase, RemainLength, MemoryRegion->Attributes);\r
-\r
- // It must be the last entry\r
- break;\r
- }\r
+ if (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE == 0 &&\r
+ RemainLength >= TT_DESCRIPTOR_SECTION_SIZE) {\r
+ // Case: Physical address aligned on the Section Size (1MB) && the length\r
+ // is greater than the Section Size\r
+ *SectionEntry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;\r
+ PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;\r
+ RemainLength -= TT_DESCRIPTOR_SECTION_SIZE;\r
} else {\r
+ PageMapLength = MIN (RemainLength, TT_DESCRIPTOR_SECTION_SIZE -\r
+ (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE));\r
+\r
+ // Case: Physical address aligned on the Section Size (1MB) && the length\r
+ // does not fill a section\r
// Case: Physical address NOT aligned on the Section Size (1MB)\r
- PopulateLevel2PageTable (SectionEntry++, PhysicalBase, RemainLength, MemoryRegion->Attributes);\r
- // Aligned the address\r
- PhysicalBase = (PhysicalBase + TT_DESCRIPTOR_SECTION_SIZE) & ~(TT_DESCRIPTOR_SECTION_SIZE-1);\r
+ PopulateLevel2PageTable (SectionEntry++, PhysicalBase, PageMapLength,\r
+ MemoryRegion->Attributes);\r
\r
// If it is the last entry\r
if (RemainLength < TT_DESCRIPTOR_SECTION_SIZE) {\r
break;\r
}\r
+\r
+ PhysicalBase += PageMapLength;\r
+ RemainLength -= PageMapLength;\r
}\r
- RemainLength -= TT_DESCRIPTOR_SECTION_SIZE;\r
}\r
}\r
\r
}\r
\r
// Translate the Memory Attributes into Translation Table Register Attributes\r
- if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) ||\r
- (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED)) {\r
- TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_NON_CACHEABLE : TTBR_NON_CACHEABLE;\r
- } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||\r
+ if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||\r
(TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) {\r
TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_BACK_ALLOC : TTBR_WRITE_BACK_ALLOC;\r
- } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) ||\r
- (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH)) {\r
- TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_THROUGH : TTBR_WRITE_THROUGH;\r
} else {\r
- ASSERT (0); // No support has been found for the attributes of the memory region that the translation table belongs to.\r
+ // Page tables must reside in memory mapped as write-back cacheable\r
+ ASSERT (0);\r
return RETURN_UNSUPPORTED;\r
}\r
\r
PageTable[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseAddress + (Index << 12)) | PageDescriptor;\r
}\r
\r
- // Flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r
- WriteBackInvalidateDataCacheRange ((VOID *)PageTable, TT_DESCRIPTOR_PAGE_SIZE);\r
-\r
// Formulate page table entry, Domain=0, NS=0\r
PageTableDescriptor = (((UINTN)PageTable) & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;\r
\r
IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
IN UINT64 Length,\r
IN UINT64 Attributes,\r
- IN EFI_PHYSICAL_ADDRESS VirtualMask,\r
OUT BOOLEAN *FlushTlbs OPTIONAL\r
)\r
{\r
// Mask in new attributes and/or permissions\r
PageTableEntry |= EntryValue;\r
\r
- if (VirtualMask != 0) {\r
- // Make this virtual address point at a physical page\r
- PageTableEntry &= ~VirtualMask;\r
- }\r
-\r
if (CurrentPageTableEntry != PageTableEntry) {\r
Mva = (VOID *)(UINTN)((((UINTN)FirstLevelIdx) << TT_DESCRIPTOR_SECTION_BASE_SHIFT) + (PageTableIndex << TT_DESCRIPTOR_PAGE_BASE_SHIFT));\r
\r
- // Clean/invalidate the cache for this page, but only\r
- // if we are modifying the memory type attributes\r
- if (((CurrentPageTableEntry ^ PageTableEntry) & TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK) != 0) {\r
- WriteBackInvalidateDataCacheRange (Mva, TT_DESCRIPTOR_PAGE_SIZE);\r
- }\r
-\r
// Only need to update if we are changing the entry\r
PageTable[PageTableIndex] = PageTableEntry;\r
ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], Mva);\r
UpdateSectionEntries (\r
IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
IN UINT64 Length,\r
- IN UINT64 Attributes,\r
- IN EFI_PHYSICAL_ADDRESS VirtualMask\r
+ IN UINT64 Attributes\r
)\r
{\r
EFI_STATUS Status = EFI_SUCCESS;\r
(FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT,\r
TT_DESCRIPTOR_SECTION_SIZE,\r
Attributes,\r
- VirtualMask,\r
NULL);\r
} else {\r
// still a section entry\r
\r
- // mask off appropriate fields\r
- Descriptor = CurrentDescriptor & ~EntryMask;\r
+ if (CurrentDescriptor != 0) {\r
+ // mask off appropriate fields\r
+ Descriptor = CurrentDescriptor & ~EntryMask;\r
+ } else {\r
+ Descriptor = ((UINTN)FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT;\r
+ }\r
\r
// mask in new attributes and/or permissions\r
Descriptor |= EntryValue;\r
- if (VirtualMask != 0) {\r
- Descriptor &= ~VirtualMask;\r
- }\r
\r
if (CurrentDescriptor != Descriptor) {\r
- Mva = (VOID *)(UINTN)(((UINTN)FirstLevelTable) << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
-\r
- // Clean/invalidate the cache for this section, but only\r
- // if we are modifying the memory type attributes\r
- if (((CurrentDescriptor ^ Descriptor) & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) != 0) {\r
- WriteBackInvalidateDataCacheRange (Mva, SIZE_1MB);\r
- }\r
+ Mva = (VOID *)(UINTN)(((UINTN)FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
\r
// Only need to update if we are changing the descriptor\r
FirstLevelTable[FirstLevelIdx + i] = Descriptor;\r
ArmSetMemoryAttributes (\r
IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
IN UINT64 Length,\r
- IN UINT64 Attributes,\r
- IN EFI_PHYSICAL_ADDRESS VirtualMask\r
+ IN UINT64 Attributes\r
)\r
{\r
EFI_STATUS Status;\r
UINT64 ChunkLength;\r
BOOLEAN FlushTlbs;\r
\r
+ if (BaseAddress > (UINT64)MAX_ADDRESS - Length + 1) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
if (Length == 0) {\r
return EFI_SUCCESS;\r
}\r
"SetMemoryAttributes(): MMU section 0x%lx length 0x%lx to %lx\n",\r
BaseAddress, ChunkLength, Attributes));\r
\r
- Status = UpdateSectionEntries (BaseAddress, ChunkLength, Attributes,\r
- VirtualMask);\r
+ Status = UpdateSectionEntries (BaseAddress, ChunkLength, Attributes);\r
\r
FlushTlbs = TRUE;\r
} else {\r
BaseAddress, ChunkLength, Attributes));\r
\r
Status = UpdatePageEntries (BaseAddress, ChunkLength, Attributes,\r
- VirtualMask, &FlushTlbs);\r
+ &FlushTlbs);\r
}\r
\r
if (EFI_ERROR (Status)) {\r
IN UINT64 Length\r
)\r
{\r
- return EFI_UNSUPPORTED;\r
+ return ArmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_XP);\r
}\r
\r
EFI_STATUS\r
IN UINT64 Length\r
)\r
{\r
- return EFI_UNSUPPORTED;\r
+ return ArmSetMemoryAttributes (BaseAddress, Length, __EFI_MEMORY_RWX);\r
}\r
\r
EFI_STATUS\r
IN UINT64 Length\r
)\r
{\r
- return EFI_UNSUPPORTED;\r
+ return ArmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_RO);\r
}\r
\r
EFI_STATUS\r
IN UINT64 Length\r
)\r
{\r
- return EFI_UNSUPPORTED;\r
+ return ArmSetMemoryAttributes (BaseAddress, Length, __EFI_MEMORY_RWX);\r
}\r
\r
RETURN_STATUS\r
projects / mirror_edk2.git / blobdiff