ArmPkg/ArmMmuLib ARM: disregard high memory when setting permissions

[mirror_edk2.git] / ArmPkg / Library / ArmMmuLib / Arm / ArmMmuLibCore.c

diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c
index 9eb6dd8d25c844d084b534c6dd9a2936d3c66c1f..bffab83d4fd0bbe1571fbab9ca3ae0c879a6357b 100644 (file)
--- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c
+++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c
@@ -135,6 +135,11 @@ PopulateLevel2PageTable (
     case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:\r
       PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_BACK;\r
       break;\r
+    case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:\r
+    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:\r
+      PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_BACK;\r
+      PageAttributes &= ~TT_DESCRIPTOR_PAGE_S_SHARED;\r
+      break;\r
     case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:\r
     case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:\r
       PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_THROUGH;\r
@@ -239,6 +244,10 @@ FillTranslationTable (
     case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:\r
       Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);\r
       break;\r
+    case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:\r
+      Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);\r
+      Attributes &= ~TT_DESCRIPTOR_SECTION_S_SHARED;\r
+      break;\r
     case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:\r
       Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);\r
       break;\r
@@ -251,6 +260,10 @@ FillTranslationTable (
     case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:\r
       Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);\r
       break;\r
+    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:\r
+      Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);\r
+      Attributes &= ~TT_DESCRIPTOR_SECTION_S_SHARED;\r
+      break;\r
     case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:\r
       Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1);\r
       break;\r
@@ -281,8 +294,8 @@ FillTranslationTable (
       PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;\r
       RemainLength -= TT_DESCRIPTOR_SECTION_SIZE;\r
     } else {\r
-      PageMapLength = MIN (RemainLength, TT_DESCRIPTOR_SECTION_SIZE) -\r
-                      (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE);\r
+      PageMapLength = MIN (RemainLength, TT_DESCRIPTOR_SECTION_SIZE -\r
+                                         (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE));\r
 \r
       // Case: Physical address aligned on the Section Size (1MB) && the length\r
       //       does not fill a section\r
@@ -343,17 +356,12 @@ ArmConfigureMmu (
   }\r
 \r
   // Translate the Memory Attributes into Translation Table Register Attributes\r
-  if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) ||\r
-      (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED)) {\r
-    TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_NON_CACHEABLE : TTBR_NON_CACHEABLE;\r
-  } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||\r
+  if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||\r
       (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) {\r
     TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_BACK_ALLOC : TTBR_WRITE_BACK_ALLOC;\r
-  } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) ||\r
-      (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH)) {\r
-    TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_THROUGH : TTBR_WRITE_THROUGH;\r
   } else {\r
-    ASSERT (0); // No support has been found for the attributes of the memory region that the translation table belongs to.\r
+    // Page tables must reside in memory mapped as write-back cacheable\r
+    ASSERT (0);\r
     return RETURN_UNSUPPORTED;\r
   }\r
 \r
@@ -461,9 +469,6 @@ ConvertSectionToPages (
     PageTable[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseAddress + (Index << 12)) | PageDescriptor;\r
   }\r
 \r
-  // Flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r
-  WriteBackInvalidateDataCacheRange ((VOID *)PageTable, TT_DESCRIPTOR_PAGE_SIZE);\r
-\r
   // Formulate page table entry, Domain=0, NS=0\r
   PageTableDescriptor = (((UINTN)PageTable) & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;\r
 \r
@@ -703,14 +708,18 @@ UpdateSectionEntries (
     } else {\r
       // still a section entry\r
 \r
-      // mask off appropriate fields\r
-      Descriptor = CurrentDescriptor & ~EntryMask;\r
+      if (CurrentDescriptor != 0) {\r
+        // mask off appropriate fields\r
+        Descriptor = CurrentDescriptor & ~EntryMask;\r
+      } else {\r
+        Descriptor = ((UINTN)FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT;\r
+      }\r
 \r
       // mask in new attributes and/or permissions\r
       Descriptor |= EntryValue;\r
 \r
       if (CurrentDescriptor  != Descriptor) {\r
-        Mva = (VOID *)(UINTN)(((UINTN)FirstLevelTable) << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
+        Mva = (VOID *)(UINTN)(((UINTN)FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
 \r
         // Only need to update if we are changing the descriptor\r
         FirstLevelTable[FirstLevelIdx + i] = Descriptor;\r
@@ -735,6 +744,10 @@ ArmSetMemoryAttributes (
   UINT64        ChunkLength;\r
   BOOLEAN       FlushTlbs;\r
 \r
+  if (BaseAddress > (UINT64)MAX_ADDRESS - Length + 1) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
   if (Length == 0) {\r
     return EFI_SUCCESS;\r
   }\r