-#/** @file
-# Arm Versatile Express package.
-#
-# Copyright (c) 2011, ARM Limited. All rights reserved.
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-[Defines]
- DEC_SPECIFICATION = 0x00010005
- PACKAGE_NAME = ArmPlatformPkg
- PACKAGE_GUID = 3308e0a0-1d94-11e0-915c-0002a5d5c51b
- PACKAGE_VERSION = 0.1
-
-################################################################################
-#
-# Include Section - list of Include Paths that are provided by this package.
-# Comments are used for Keywords and Module Types.
-#
-# Supported Module Types:
-# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
-#
-################################################################################
-[Includes.common]
- Include # Root include for the package
-
-[Guids.common]
- gArmPlatformTokenSpaceGuid = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }
- #
- # Following Guid must match FILE_GUID in MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
- #
- gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } }
-
-[PcdsFeatureFlag.common]
- # Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0.
- gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012
-
- gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE|BOOLEAN|0x00000001
- gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|FALSE|BOOLEAN|0x00000002
- gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004
-
-
-[PcdsFixedAtBuild.common]
- # These PCDs should be FeaturePcds. But we used these PCDs as an '#if' in an ASM file.
- # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
- gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|0|UINT32|0x00000003
- gArmPlatformTokenSpaceGuid.PcdMPCoreMaxCores|1|UINT32|0x0000002D
-
- # Stack for CPU Cores in Secure Mode
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT32|0x00000005
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize|0|UINT32|0x00000006
-
- # Stack for CPU Cores in Secure Monitor Mode
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0|UINT32|0x00000008
-
- # Stack for CPU Cores in Non Secure Mode
- gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase|0|UINT32|0x00000009
- gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize|0|UINT32|0x0000000A
-
- # Size of the region used by UEFI in permanent memory (Reserved 128MB by default)
- gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015
-
- # Size to reserve in the primary core stack for PEI Global Variables
- # = sizeof(UINTN) /* PcdPeiServicePtr or HobListPtr */
- gArmPlatformTokenSpaceGuid.PcdPeiGlobalVariableSize|0x4|UINT32|0x00000016
- # PeiServicePtr and HobListPtr shares the same location in the PEI Global Variable list
- # PeiServicePtr is only valid with PEI Core and HobListPtr only when the PEI Core is skipped.
- gArmPlatformTokenSpaceGuid.PcdPeiServicePtrGlobalOffset|0x4|UINT32|0x00000017
- gArmPlatformTokenSpaceGuid.PcdHobListPtrGlobalOffset|0x4|UINT32|0x00000018
-
- #
- # ARM Primecells
- #
-
- ## SP804 DualTimer
- gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz|1|UINT32|0x0000001D
- gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|0|UINT32|0x0000001E
- gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0|UINT32|0x0000002A
- gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0|UINT32|0x0000002B
- gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0|UINT32|0x0000002C
-
- ## SP805 Watchdog
- gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0|UINT32|0x00000023
- gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021
-
- ## PL011 UART
- gArmPlatformTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0x00000000|UINT32|0x0000001F
- gArmPlatformTokenSpaceGuid.PcdUartDefaultTimeout|0x00000000|UINT32|0x00000020
-
- ## PL031 RealTimeClock
- gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024
- gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022
-
- ## PL061 GPIO
- gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025
-
- ## PL111 Lcd
- gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026
- gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027
-
- ## PL180 MCI
- gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000028
- gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000029
-
- #
- # BDS - Boot Manager
- #
- gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Platform"|VOID*|0x00000019
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Default Boot Device"|VOID*|0x0000000C
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L""|VOID*|0x0000000D
- gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L""|VOID*|0x0000000E
- gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|""|VOID*|0x000000F
- # PcdDefaultBootType define the type of the binary pointed by PcdDefaultBootDevicePath:
- # - 0 = an EFI application
- # - 1 = a Linux kernel with ATAG support
- # - 2 = a Linux kernel with FDT support
- gArmPlatformTokenSpaceGuid.PcdDefaultBootType|0|UINT32|0x00000010
- gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L""|VOID*|0x00000011
-
- ## Timeout value for displaying progressing bar in before boot OS.
- # According to UEFI 2.0 spec, the default TimeOut should be 0xffff.
- gArmPlatformTokenSpaceGuid.PcdPlatformBootTimeOut|0xffff|UINT16|0x0000001A
-
- gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L""|VOID*|0x0000001B
- gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L""|VOID*|0x0000001C
-
+#/** @file\r
+#\r
+# Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#**/\r
+\r
+[Defines]\r
+ DEC_SPECIFICATION = 0x00010005\r
+ PACKAGE_NAME = ArmPlatformPkg\r
+ PACKAGE_GUID = 3308e0a0-1d94-11e0-915c-0002a5d5c51b\r
+ PACKAGE_VERSION = 0.1\r
+\r
+################################################################################\r
+#\r
+# Include Section - list of Include Paths that are provided by this package.\r
+# Comments are used for Keywords and Module Types.\r
+#\r
+# Supported Module Types:\r
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
+#\r
+################################################################################\r
+[Includes.common]\r
+ Include # Root include for the package\r
+\r
+[Guids.common]\r
+ gArmPlatformTokenSpaceGuid = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }\r
+ #\r
+ # Following Guid must match FILE_GUID in MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r
+ #\r
+ gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } }\r
+ #\r
+ # Following Guid must match FILE_GUID in SecurityPkg/VariableAuthenticated/RuntimeDxe/VariableRuntimeDxe.inf\r
+ #\r
+ gVariableAuthenticatedRuntimeDxeFileGuid = { 0x2226f30f, 0x3d5b, 0x402d, {0x99, 0x36, 0xa9, 0x71, 0x84, 0xEB, 0x45, 0x16 } }\r
+\r
+ ## Include/Guid/ArmGlobalVariableHob.h\r
+ gArmGlobalVariableGuid = { 0xc3253c90, 0xa24f, 0x4599, { 0xa6, 0x64, 0x1f, 0x88, 0x13, 0x77, 0x8f, 0xc9} }\r
+\r
+ gArmBootMonFsFileInfoGuid = { 0x41e26b9c, 0xada6, 0x45b3, { 0x80, 0x8e, 0x23, 0x57, 0xa3, 0x5b, 0x60, 0xd6 } }\r
+\r
+[Ppis]\r
+ ## Include/Ppi/ArmGlobalVariable.h\r
+ gArmGlobalVariablePpiGuid = { 0xab1c1816, 0xd542, 0x4e6f, {0x9b, 0x1e, 0x8e, 0xcd, 0x92, 0x53, 0xe2, 0xe7} }\r
+\r
+[PcdsFeatureFlag.common]\r
+ # Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0.\r
+ gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012\r
+\r
+ gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE|BOOLEAN|0x00000001\r
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|FALSE|BOOLEAN|0x00000002\r
+ gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004\r
+\r
+ gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked|FALSE|BOOLEAN|0x0000003C\r
+\r
+ # Disable the GOP controller on ExitBootServices(). By default the value is FALSE,\r
+ # we assume the OS will handle the FrameBuffer from the UEFI GOP information.\r
+ gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices|FALSE|BOOLEAN|0x0000003D\r
+\r
+[PcdsFixedAtBuild.common]\r
+ gArmPlatformTokenSpaceGuid.PcdCoreCount|1|UINT32|0x00000039\r
+ gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038\r
+\r
+ # Stack for CPU Cores in Secure Mode\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT32|0x00000005\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000|UINT32|0x00000036\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006\r
+\r
+ # Stack for CPU Cores in Non Secure Mode\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT64|0x00000009\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000|UINT32|0x0000000A\r
+\r
+ # Size of the region used by UEFI in permanent memory (Reserved 128MB by default)\r
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015\r
+\r
+ # Size to reserve in the primary core stack for PEI Global Variables\r
+ # = sizeof(UINTN) /* PcdPeiServicePtr or HobListPtr */\r
+ gArmPlatformTokenSpaceGuid.PcdPeiGlobalVariableSize|0x4|UINT32|0x00000016\r
+ # PeiServicePtr and HobListPtr shares the same location in the PEI Global Variable list\r
+ # PeiServicePtr is only valid with PEI Core and HobListPtr only when the PEI Core is skipped.\r
+ gArmPlatformTokenSpaceGuid.PcdPeiServicePtrGlobalOffset|0x0|UINT32|0x00000017\r
+ gArmPlatformTokenSpaceGuid.PcdHobListPtrGlobalOffset|0x0|UINT32|0x00000018\r
+\r
+ # Size to reserve in the primary core stack for SEC Global Variables\r
+ gArmPlatformTokenSpaceGuid.PcdSecGlobalVariableSize|0x0|UINT32|0x00000031\r
+\r
+ # Boot Monitor FileSystem\r
+ gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L""|VOID*|0x0000003A\r
+\r
+ #\r
+ # ARM Primecells\r
+ #\r
+\r
+ ## SP804 DualTimer\r
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz|1|UINT32|0x0000001D\r
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|0|UINT32|0x0000001E\r
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0|UINT32|0x0000002A\r
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0|UINT32|0x0000002B\r
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0|UINT32|0x0000002C\r
+\r
+ ## SP805 Watchdog\r
+ gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0|UINT32|0x00000023\r
+ gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021\r
+\r
+ ## PL011 UART\r
+ gArmPlatformTokenSpaceGuid.PL011UartClkInHz|24000000|UINT32|0x0000001F\r
+ gArmPlatformTokenSpaceGuid.PL011UartInteger|0|UINT32|0x00000020\r
+ gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D\r
+\r
+ ## PL061 GPIO\r
+ gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025\r
+\r
+ ## PL111 Lcd & HdLcd\r
+ gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026\r
+ gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027\r
+\r
+ ## PL180 MCI\r
+ gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000028\r
+ gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000029\r
+\r
+ #\r
+ # BDS - Boot Manager\r
+ #\r
+ gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Platform"|VOID*|0x00000019\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Default Boot Device"|VOID*|0x0000000C\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L""|VOID*|0x0000000D\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L""|VOID*|0x0000000E\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|L""|VOID*|0x000000F\r
+ # PcdDefaultBootType define the type of the binary pointed by PcdDefaultBootDevicePath:\r
+ # - 0 = an EFI application\r
+ # - 1 = a Linux kernel with ATAG support\r
+ # - 2 = a Linux kernel with FDT support\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootType|0|UINT32|0x00000010\r
+\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L""|VOID*|0x0000001B\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L""|VOID*|0x0000001C\r
+\r
+[PcdsFixedAtBuild.common,PcdsDynamic.common]\r
+ ## PL031 RealTimeClock\r
+ gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024\r
+ gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022\r
+\r
+ #\r
+ # Inclusive range of allowed PCI buses.\r
+ #\r
+ gArmPlatformTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x0000003E\r
+ gArmPlatformTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000003F\r
+\r
+ #\r
+ # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.\r
+ # Note that "IO" is just another MMIO range that simulates IO space; there\r
+ # are no special instructions to access it.\r
+ #\r
+ # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are\r
+ # specific to their containing address spaces. In order to get the physical\r
+ # address for the CPU, for a given access, the respective translation value\r
+ # has to be added.\r
+ #\r
+ # The translations always have to be initialized like this, using UINT64:\r
+ #\r
+ # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space\r
+ # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space\r
+ # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space\r
+ #\r
+ # PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;\r
+ # PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;\r
+ # PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;\r
+ #\r
+ # because (a) the target address space (ie. the cpu-physical space) is\r
+ # 64-bit, and (b) the translation values are meant as offsets for *modular*\r
+ # arithmetic.\r
+ #\r
+ # Accordingly, the translation itself needs to be implemented as:\r
+ #\r
+ # UINT64 UntranslatedIoAddress; // input parameter\r
+ # UINT32 UntranslatedMmio32Address; // input parameter\r
+ # UINT64 UntranslatedMmio64Address; // input parameter\r
+ #\r
+ # UINT64 TranslatedIoAddress; // output parameter\r
+ # UINT64 TranslatedMmio32Address; // output parameter\r
+ # UINT64 TranslatedMmio64Address; // output parameter\r
+ #\r
+ # TranslatedIoAddress = UntranslatedIoAddress +\r
+ # PcdPciIoTranslation;\r
+ # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +\r
+ # PcdPciMmio32Translation;\r
+ # TranslatedMmio64Address = UntranslatedMmio64Address +\r
+ # PcdPciMmio64Translation;\r
+ #\r
+ # The modular arithmetic performed in UINT64 ensures that the translation\r
+ # works correctly regardless of the relation between IoCpuBase and\r
+ # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and\r
+ # PcdPciMmio64Base.\r
+ #\r
+ gArmPlatformTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000040\r
+ gArmPlatformTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000041\r
+ gArmPlatformTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000042\r
+ gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000043\r
+ gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000044\r
+ gArmPlatformTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000045\r
+ gArmPlatformTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000046\r
+ gArmPlatformTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000047\r
+ gArmPlatformTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000048\r
+\r
+[PcdsFixedAtBuild.ARM]\r
+ # Stack for CPU Cores in Secure Monitor Mode\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008\r
+\r
+[PcdsFixedAtBuild.AARCH64]\r
+ # The Secure World is only running in EL3. Only one set of stacks is needed for AArch64.\r
+ # The Secure stacks are described by PcdCPUCoresSecStackBase, PcdCPUCoreSecPrimaryStackSize\r
+ # and PcdCPUCoreSecSecondaryStackSize\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x0|UINT32|0x00000008\r
+\r
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