ArmPlatformPkg/ArmRealViewEb: Add support for PL111 Lcd controller

[mirror_edk2.git] / ArmPlatformPkg / ArmRealViewEbPkg / Include / Platform / ArmPlatform.h

diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform/ArmPlatform.h b/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform/ArmPlatform.h
index 17f198373de6a8bc86ee3eaf54d569d574fa4daa..18f8a66502b5098b07c64b48cc96bff8b991fef7 100644 (file)
--- a/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform/ArmPlatform.h
+++ b/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform/ArmPlatform.h
@@ -21,79 +21,85 @@
 *******************************************/\r
 \r
 // Can be NOR, DOC, DRAM, SRAM\r
-#define ARM_EB_REMAP_BASE                       0x00000000\r
-#define ARM_EB_REMAP_SZ                         0x04000000\r
+#define ARM_EB_REMAP_BASE                     0x00000000\r
+#define ARM_EB_REMAP_SZ                       0x04000000\r
 \r
 // Motherboard Peripheral and On-chip peripheral\r
-#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE       0x10000000\r
-#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ         0x00100000\r
-#define ARM_EB_BOARD_PERIPH_BASE                0x10000000\r
-//#define ARM_EB_CHIP_PERIPH_BASE                 0x10020000\r
+#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE     0x10000000\r
+#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ       0x00100000\r
+#define ARM_EB_BOARD_PERIPH_BASE              0x10000000\r
+//#define ARM_EB_CHIP_PERIPH_BASE             0x10020000\r
 \r
 // SMC\r
-#define ARM_EB_SMC_BASE                         0x40000000\r
-#define ARM_EB_SMC_SZ                           0x20000000\r
+#define ARM_EB_SMC_BASE                       0x40000000\r
+#define ARM_EB_SMC_SZ                         0x20000000\r
 \r
 // NOR Flash 1\r
-#define ARM_EB_SMB_NOR_BASE                     0x40000000\r
-#define ARM_EB_SMB_NOR_SZ                       0x04000000 /* 64 MB */\r
+#define ARM_EB_SMB_NOR_BASE                   0x40000000\r
+#define ARM_EB_SMB_NOR_SZ                     0x04000000 /* 64 MB */\r
 // DOC Flash\r
-#define ARM_EB_SMB_DOC_BASE                     0x44000000\r
-#define ARM_EB_SMB_DOC_SZ                       0x04000000 /* 64 MB */\r
+#define ARM_EB_SMB_DOC_BASE                   0x44000000\r
+#define ARM_EB_SMB_DOC_SZ                     0x04000000 /* 64 MB */\r
 // SRAM\r
-#define ARM_EB_SMB_SRAM_BASE                    0x48000000\r
-#define ARM_EB_SMB_SRAM_SZ                      0x02000000 /* 32 MB */\r
+#define ARM_EB_SMB_SRAM_BASE                  0x48000000\r
+#define ARM_EB_SMB_SRAM_SZ                    0x02000000 /* 32 MB */\r
 // USB, Ethernet, VRAM\r
-#define ARM_EB_SMB_PERIPH_BASE                  0x4E000000\r
-//#define ARM_EB_SMB_PERIPH_VRAM                  0x4C000000\r
-#define ARM_EB_SMB_PERIPH_SZ                    0x02000000 /* 32 MB */\r
+#define ARM_EB_SMB_PERIPH_BASE                0x4E000000\r
+//#define ARM_EB_SMB_PERIPH_VRAM              0x4C000000\r
+#define ARM_EB_SMB_PERIPH_SZ                  0x02000000 /* 32 MB */\r
 \r
 // DRAM\r
-#define ARM_EB_DRAM_BASE                        0x70000000\r
-#define ARM_EB_DRAM_SZ                          0x10000000\r
+#define ARM_EB_DRAM_BASE                      0x70000000\r
+#define ARM_EB_DRAM_SZ                        0x10000000\r
 \r
 // Logic Tile\r
-#define ARM_EB_LOGIC_TILE_BASE                     0xC0000000\r
-#define ARM_EB_LOGIC_TILE_SZ                       0x40000000\r
+#define ARM_EB_LOGIC_TILE_BASE                0xC0000000\r
+#define ARM_EB_LOGIC_TILE_SZ                  0x40000000\r
 \r
 /*******************************************\r
 // Motherboard peripherals\r
 *******************************************/\r
 \r
 // Define MotherBoard SYS flags offsets (from ARM_EB_BOARD_PERIPH_BASE)\r
-#define ARM_EB_SYS_FLAGS_REG                    (ARM_EB_BOARD_PERIPH_BASE + 0x00030)\r
-#define ARM_EB_SYS_FLAGS_SET_REG                (ARM_EB_BOARD_PERIPH_BASE + 0x00030)\r
-#define ARM_EB_SYS_FLAGS_CLR_REG                (ARM_EB_BOARD_PERIPH_BASE + 0x00034)\r
-#define ARM_EB_SYS_FLAGS_NV_REG                 (ARM_EB_BOARD_PERIPH_BASE + 0x00038)\r
-#define ARM_EB_SYS_FLAGS_NV_SET_REG             (ARM_EB_BOARD_PERIPH_BASE + 0x00038)\r
-#define ARM_EB_SYS_FLAGS_NV_CLR_REG             (ARM_EB_BOARD_PERIPH_BASE + 0x0003C)\r
-#define ARM_EB_SYS_PROCID0_REG                  (ARM_EB_BOARD_PERIPH_BASE + 0x00084)\r
-#define ARM_EB_SYS_PROCID1_REG                  (ARM_EB_BOARD_PERIPH_BASE + 0x00088)\r
-#define ARM_EB_SYS_CFGDATA_REG                  (ARM_EB_BOARD_PERIPH_BASE + 0x000A0)\r
-#define ARM_EB_SYS_CFGCTRL_REG                  (ARM_EB_BOARD_PERIPH_BASE + 0x000A4)\r
-#define ARM_EB_SYS_CFGSTAT_REG                  (ARM_EB_BOARD_PERIPH_BASE + 0x000A8)\r
+#define ARM_EB_SYS_OSC4_REG                   (ARM_EB_BOARD_PERIPH_BASE + 0x0001C)\r
+#define ARM_EB_SYS_LOCK_REG                   (ARM_EB_BOARD_PERIPH_BASE + 0x00020)\r
+#define ARM_EB_SYS_100HZ_REG                  (ARM_EB_BOARD_PERIPH_BASE + 0x00024)\r
+#define ARM_EB_SYS_FLAGS_REG                  (ARM_EB_BOARD_PERIPH_BASE + 0x00030)\r
+#define ARM_EB_SYS_FLAGS_SET_REG              (ARM_EB_BOARD_PERIPH_BASE + 0x00030)\r
+#define ARM_EB_SYS_FLAGS_CLR_REG              (ARM_EB_BOARD_PERIPH_BASE + 0x00034)\r
+#define ARM_EB_SYS_FLAGS_NV_REG               (ARM_EB_BOARD_PERIPH_BASE + 0x00038)\r
+#define ARM_EB_SYS_FLAGS_NV_SET_REG           (ARM_EB_BOARD_PERIPH_BASE + 0x00038)\r
+#define ARM_EB_SYS_FLAGS_NV_CLR_REG           (ARM_EB_BOARD_PERIPH_BASE + 0x0003C)\r
+#define ARM_EB_SYS_CLCD_REG                   (ARM_EB_BOARD_PERIPH_BASE + 0x00050)\r
+#define ARM_EB_SYS_PROCID0_REG                (ARM_EB_BOARD_PERIPH_BASE + 0x00084)\r
+#define ARM_EB_SYS_PROCID1_REG                (ARM_EB_BOARD_PERIPH_BASE + 0x00088)\r
+#define ARM_EB_SYS_CFGDATA_REG                (ARM_EB_BOARD_PERIPH_BASE + 0x000A0)\r
+#define ARM_EB_SYS_CFGCTRL_REG                (ARM_EB_BOARD_PERIPH_BASE + 0x000A4)\r
+#define ARM_EB_SYS_CFGSTAT_REG                (ARM_EB_BOARD_PERIPH_BASE + 0x000A8)\r
 \r
 // SP810 Controller\r
-#define SP810_CTRL_BASE                      (ARM_EB_BOARD_PERIPH_BASE + 0x01000)\r
+#define SP810_CTRL_BASE                       (ARM_EB_BOARD_PERIPH_BASE + 0x01000)\r
 \r
 // SYSTRCL Register\r
-#define ARM_EB_SYSCTRL                                                                                 0x10001000\r
+#define ARM_EB_SYSCTRL                                                                                   0x10001000\r
 \r
 // Uart0\r
-#define PL011_CONSOLE_UART_BASE                (ARM_EB_BOARD_PERIPH_BASE + 0x09000)\r
-#define PL011_CONSOLE_UART_SPEED            115200\r
+#define PL011_CONSOLE_UART_BASE               (ARM_EB_BOARD_PERIPH_BASE + 0x09000)\r
 \r
 // SP804 Timer Bases\r
-#define SP804_TIMER0_BASE                    (ARM_EB_BOARD_PERIPH_BASE + 0x11000)\r
-#define SP804_TIMER1_BASE                    (ARM_EB_BOARD_PERIPH_BASE + 0x11020)\r
-#define SP804_TIMER2_BASE                    (ARM_EB_BOARD_PERIPH_BASE + 0x12000)\r
-#define SP804_TIMER3_BASE                    (ARM_EB_BOARD_PERIPH_BASE + 0x12020)\r
+#define SP804_TIMER0_BASE                     (ARM_EB_BOARD_PERIPH_BASE + 0x11000)\r
+#define SP804_TIMER1_BASE                     (ARM_EB_BOARD_PERIPH_BASE + 0x11020)\r
+#define SP804_TIMER2_BASE                     (ARM_EB_BOARD_PERIPH_BASE + 0x12000)\r
+#define SP804_TIMER3_BASE                     (ARM_EB_BOARD_PERIPH_BASE + 0x12020)\r
 \r
 // Dynamic Memory Controller Base\r
 #define ARM_EB_DMC_BASE                     0x10018000\r
 \r
 // Static Memory Controller Base\r
 #define ARM_EB_SMC_CTRL_BASE                    0x10080000\r
+#define PL111_CLCD_BASE                       0x10020000\r
+//Note: Moving the framebuffer into the 0x70000000-0x80000000 region does not seem to work\r
+#define PL111_CLCD_VRAM_BASE                  0x00100000\r
 \r
 /*// System Configuration Controller register Base addresses\r
 //#define ARM_EB_SYS_CFG_CTRL_BASE                0x100E2000\r