// L2x0 Cache Controller Base Address\r
//#define ARM_EB_L2x0_CTLR_BASE 0x1E00A000*/\r
\r
+#define ARM_EB_SYS_PROC_ID_MASK (0xFF << 24)\r
+#define ARM_EB_SYS_PROC_ID_CORTEX_A8 (0x0E << 24)\r
+#define ARM_EB_SYS_PROC_ID_CORTEX_A9 (0x0C << 24)\r
\r
/*******************************************\r
// EFI Memory Map in Permanent Memory (DRAM)\r