-/** @file
-*
-* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include <Library/IoLib.h>
-#include <Library/ArmLib.h>
-#include <Library/ArmPlatformLib.h>
-#include <Library/DebugLib.h>
-#include <Library/PcdLib.h>
-
-#include <Drivers/PL341Dmc.h>
-#include <Drivers/SP804Timer.h>
-
-#include <Ppi/ArmMpCoreInfo.h>
-
-#include <ArmPlatform.h>
-
-ARM_CORE_INFO mRealViewEbMpCoreInfoTable[] = {
- {
- // Cluster 0, Core 0
- 0x0, 0x0,
-
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value
- (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_REG,
- (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_SET_REG,
- (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_CLR_REG,
- (UINT64)0xFFFFFFFF
- },
- {
- // Cluster 0, Core 1
- 0x0, 0x1,
-
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value
- (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_REG,
- (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_SET_REG,
- (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_CLR_REG,
- (UINT64)0xFFFFFFFF
- }
-};
-
-/**
- Return the current Boot Mode
-
- This function returns the boot reason on the platform
-
-**/
-EFI_BOOT_MODE
-ArmPlatformGetBootMode (
- VOID
- )
-{
- return BOOT_WITH_FULL_CONFIGURATION;
-}
-
-/**
- Initialize controllers that must setup in the normal world
-
- This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
- in the PEI phase.
-
-**/
-RETURN_STATUS
-ArmPlatformInitialize (
- IN UINTN MpId
- )
-{
- if (!IS_PRIMARY_CORE(MpId)) {
- return RETURN_SUCCESS;
- }
-
- // Disable memory remapping and return to normal mapping
- MmioOr32 (ARM_EB_SYSCTRL, BIT8); //EB_SP810_CTRL_BASE
-
- // Configure periodic timer (TIMER0) for 1MHz operation
- MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);
- // Configure 1MHz clock
- MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);
- // configure SP810 to use 1MHz clock and disable
- MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
- // Configure SP810 to use 1MHz clock and disable
- MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
-
- return RETURN_SUCCESS;
-}
-
-/**
- Initialize the system (or sometimes called permanent) memory
-
- This memory is generally represented by the DRAM.
-
-**/
-VOID
-ArmPlatformInitializeSystemMemory (
- VOID
- )
-{
- // We do not need to initialize the System Memory on RTSM
-}
-
-EFI_STATUS
-PrePeiCoreGetMpCoreInfo (
- OUT UINTN *CoreCount,
- OUT ARM_CORE_INFO **ArmCoreTable
- )
-{
- if ((MmioRead32 (ARM_EB_SYS_PROCID0_REG) & ARM_EB_SYS_PROC_ID_MASK) == ARM_EB_SYS_PROC_ID_CORTEX_A9) {
- *CoreCount = sizeof(mRealViewEbMpCoreInfoTable) / sizeof(ARM_CORE_INFO);
- *ArmCoreTable = mRealViewEbMpCoreInfoTable;
- return EFI_SUCCESS;
- } else {
- return EFI_UNSUPPORTED;
- }
-}
-
-// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
-EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
-ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
-
-EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
- {
- EFI_PEI_PPI_DESCRIPTOR_PPI,
- &mArmMpCoreInfoPpiGuid,
- &mMpCoreInfoPpi
- }
-};
-
-VOID
-ArmPlatformGetPlatformPpiList (
- OUT UINTN *PpiListSize,
- OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
- )
-{
- *PpiListSize = sizeof(gPlatformPpiTable);
- *PpiList = gPlatformPpiTable;
-}
-
+/** @file\r
+*\r
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+* \r
+* This program and the accompanying materials \r
+* are licensed and made available under the terms and conditions of the BSD License \r
+* which accompanies this distribution. The full text of the license may be found at \r
+* http://opensource.org/licenses/bsd-license.php \r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+*\r
+**/\r
+\r
+#include <Library/IoLib.h>\r
+#include <Library/ArmLib.h>\r
+#include <Library/ArmPlatformLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+#include <Drivers/PL341Dmc.h>\r
+#include <Drivers/SP804Timer.h>\r
+\r
+#include <Ppi/ArmMpCoreInfo.h>\r
+\r
+#include <ArmPlatform.h>\r
+\r
+ARM_CORE_INFO mRealViewEbMpCoreInfoTable[] = {\r
+ {\r
+ // Cluster 0, Core 0\r
+ 0x0, 0x0,\r
+\r
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
+ (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_REG,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_SET_REG,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_CLR_REG,\r
+ (UINT64)0xFFFFFFFF\r
+ },\r
+ {\r
+ // Cluster 0, Core 1\r
+ 0x0, 0x1,\r
+\r
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
+ (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_REG,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_SET_REG,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_CLR_REG,\r
+ (UINT64)0xFFFFFFFF\r
+ }\r
+};\r
+\r
+/**\r
+ Return the current Boot Mode\r
+\r
+ This function returns the boot reason on the platform\r
+\r
+**/\r
+EFI_BOOT_MODE\r
+ArmPlatformGetBootMode (\r
+ VOID\r
+ )\r
+{\r
+ return BOOT_WITH_FULL_CONFIGURATION;\r
+}\r
+\r
+/**\r
+ Initialize controllers that must setup in the normal world\r
+\r
+ This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei\r
+ in the PEI phase.\r
+\r
+**/\r
+RETURN_STATUS\r
+ArmPlatformInitialize (\r
+ IN UINTN MpId\r
+ )\r
+{\r
+ if (!IS_PRIMARY_CORE(MpId)) {\r
+ return RETURN_SUCCESS;\r
+ }\r
+\r
+ // Disable memory remapping and return to normal mapping\r
+ MmioOr32 (ARM_EB_SYSCTRL, BIT8); //EB_SP810_CTRL_BASE\r
+\r
+ // Configure periodic timer (TIMER0) for 1MHz operation\r
+ MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);\r
+ // Configure 1MHz clock\r
+ MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);\r
+ // configure SP810 to use 1MHz clock and disable\r
+ MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);\r
+ // Configure SP810 to use 1MHz clock and disable\r
+ MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);\r
+\r
+ return RETURN_SUCCESS;\r
+}\r
+\r
+/**\r
+ Initialize the system (or sometimes called permanent) memory\r
+\r
+ This memory is generally represented by the DRAM.\r
+\r
+**/\r
+VOID\r
+ArmPlatformInitializeSystemMemory (\r
+ VOID\r
+ )\r
+{\r
+ // We do not need to initialize the System Memory on RTSM\r
+}\r
+\r
+EFI_STATUS\r
+PrePeiCoreGetMpCoreInfo (\r
+ OUT UINTN *CoreCount,\r
+ OUT ARM_CORE_INFO **ArmCoreTable\r
+ )\r
+{\r
+ if ((MmioRead32 (ARM_EB_SYS_PROCID0_REG) & ARM_EB_SYS_PROC_ID_MASK) == ARM_EB_SYS_PROC_ID_CORTEX_A9) {\r
+ *CoreCount = sizeof(mRealViewEbMpCoreInfoTable) / sizeof(ARM_CORE_INFO);\r
+ *ArmCoreTable = mRealViewEbMpCoreInfoTable;\r
+ return EFI_SUCCESS;\r
+ } else {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+}\r
+\r
+// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore\r
+EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;\r
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };\r
+\r
+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {\r
+ {\r
+ EFI_PEI_PPI_DESCRIPTOR_PPI,\r
+ &mArmMpCoreInfoPpiGuid,\r
+ &mMpCoreInfoPpi\r
+ }\r
+};\r
+\r
+VOID\r
+ArmPlatformGetPlatformPpiList (\r
+ OUT UINTN *PpiListSize,\r
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList\r
+ )\r
+{\r
+ *PpiListSize = sizeof(gPlatformPpiTable);\r
+ *PpiList = gPlatformPpiTable;\r
+}\r
+\r
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