+++ /dev/null
-/** @file\r
- This file implement the MMC Host Protocol for the ARM PrimeCell PL180.\r
-\r
- Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
-**/\r
-\r
-#include "PL180Mci.h"\r
-\r
-#include <Library/DevicePathLib.h>\r
-#include <Library/BaseMemoryLib.h>\r
-\r
-EFI_MMC_HOST_PROTOCOL *gpMmcHost;\r
-\r
-// Untested ...\r
-//#define USE_STREAM\r
-\r
-#define MMCI0_BLOCKLEN 512\r
-#define MMCI0_POW2_BLOCKLEN 9\r
-#define MMCI0_TIMEOUT 1000\r
-\r
-#define SYS_MCI_CARDIN BIT0\r
-#define SYS_MCI_WPROT BIT1\r
-\r
-BOOLEAN\r
-MciIsPowerOn (\r
- VOID\r
- )\r
-{\r
- return ((MmioRead32 (MCI_POWER_CONTROL_REG) & MCI_POWER_ON) == MCI_POWER_ON);\r
-}\r
-\r
-EFI_STATUS\r
-MciInitialize (\r
- VOID\r
- )\r
-{\r
- MCI_TRACE ("MciInitialize()");\r
- return EFI_SUCCESS;\r
-}\r
-\r
-BOOLEAN\r
-MciIsCardPresent (\r
- IN EFI_MMC_HOST_PROTOCOL *This\r
- )\r
-{\r
- return (MmioRead32 (FixedPcdGet32 (PcdPL180SysMciRegAddress)) & SYS_MCI_CARDIN);\r
-}\r
-\r
-BOOLEAN\r
-MciIsReadOnly (\r
- IN EFI_MMC_HOST_PROTOCOL *This\r
- )\r
-{\r
- return (MmioRead32 (FixedPcdGet32 (PcdPL180SysMciRegAddress)) & SYS_MCI_WPROT);\r
-}\r
-\r
-// Convert block size to 2^n\r
-STATIC\r
-UINT32\r
-GetPow2BlockLen (\r
- IN UINT32 BlockLen\r
- )\r
-{\r
- UINTN Loop;\r
- UINTN Pow2BlockLen;\r
-\r
- Loop = 0x8000;\r
- Pow2BlockLen = 15;\r
- do {\r
- Loop = (Loop >> 1) & 0xFFFF;\r
- Pow2BlockLen--;\r
- } while (Pow2BlockLen && (!(Loop & BlockLen)));\r
-\r
- return Pow2BlockLen;\r
-}\r
-\r
-VOID\r
-MciPrepareDataPath (\r
- IN UINTN TransferDirection\r
- )\r
-{\r
- // Set Data Length & Data Timer\r
- MmioWrite32 (MCI_DATA_TIMER_REG, 0xFFFFFFF);\r
- MmioWrite32 (MCI_DATA_LENGTH_REG, MMCI0_BLOCKLEN);\r
-\r
-#ifndef USE_STREAM\r
- //Note: we are using a hardcoded BlockLen (==512). If we decide to use a variable size, we could\r
- // compute the pow2 of BlockLen with the above function GetPow2BlockLen ()\r
- MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_DMA_ENABLE | TransferDirection | (MMCI0_POW2_BLOCKLEN << 4));\r
-#else\r
- MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_DMA_ENABLE | TransferDirection | MCI_DATACTL_STREAM_TRANS);\r
-#endif\r
-}\r
-\r
-EFI_STATUS\r
-MciSendCommand (\r
- IN EFI_MMC_HOST_PROTOCOL *This,\r
- IN MMC_CMD MmcCmd,\r
- IN UINT32 Argument\r
- )\r
-{\r
- UINT32 Status;\r
- UINT32 Cmd;\r
- UINTN RetVal;\r
- UINTN CmdCtrlReg;\r
- UINT32 DoneMask;\r
-\r
- RetVal = EFI_SUCCESS;\r
-\r
- if ((MmcCmd == MMC_CMD17) || (MmcCmd == MMC_CMD11)) {\r
- MciPrepareDataPath (MCI_DATACTL_CARD_TO_CONT);\r
- } else if ((MmcCmd == MMC_CMD24) || (MmcCmd == MMC_CMD20)) {\r
- MciPrepareDataPath (MCI_DATACTL_CONT_TO_CARD);\r
- } else if (MmcCmd == MMC_CMD6) {\r
- MmioWrite32 (MCI_DATA_TIMER_REG, 0xFFFFFFF);\r
- MmioWrite32 (MCI_DATA_LENGTH_REG, 64);\r
-#ifndef USE_STREAM\r
- MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_CARD_TO_CONT | GetPow2BlockLen (64));\r
-#else\r
- MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_CARD_TO_CONT | MCI_DATACTL_STREAM_TRANS);\r
-#endif\r
- } else if (MmcCmd == MMC_ACMD51) {\r
- MmioWrite32 (MCI_DATA_TIMER_REG, 0xFFFFFFF);\r
- /* SCR register is 8 bytes long. */\r
- MmioWrite32 (MCI_DATA_LENGTH_REG, 8);\r
-#ifndef USE_STREAM\r
- MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_CARD_TO_CONT | GetPow2BlockLen (8));\r
-#else\r
- MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_CARD_TO_CONT | MCI_DATACTL_STREAM_TRANS);\r
-#endif\r
- }\r
-\r
- // Create Command for PL180\r
- Cmd = (MMC_GET_INDX (MmcCmd) & INDX_MASK) | MCI_CPSM_ENABLE;\r
- if (MmcCmd & MMC_CMD_WAIT_RESPONSE) {\r
- Cmd |= MCI_CPSM_WAIT_RESPONSE;\r
- }\r
-\r
- if (MmcCmd & MMC_CMD_LONG_RESPONSE) {\r
- Cmd |= MCI_CPSM_LONG_RESPONSE;\r
- }\r
-\r
- // Clear Status register static flags\r
- MmioWrite32 (MCI_CLEAR_STATUS_REG, MCI_CLR_ALL_STATUS);\r
-\r
- // Write to command argument register\r
- MmioWrite32 (MCI_ARGUMENT_REG, Argument);\r
-\r
- // Write to command register\r
- MmioWrite32 (MCI_COMMAND_REG, Cmd);\r
-\r
- DoneMask = (Cmd & MCI_CPSM_WAIT_RESPONSE)\r
- ? (MCI_STATUS_CMD_RESPEND | MCI_STATUS_CMD_ERROR)\r
- : (MCI_STATUS_CMD_SENT | MCI_STATUS_CMD_ERROR);\r
- do {\r
- Status = MmioRead32 (MCI_STATUS_REG);\r
- } while (! (Status & DoneMask));\r
-\r
- if ((Status & MCI_STATUS_CMD_ERROR)) {\r
- // Clear Status register error flags\r
- MmioWrite32 (MCI_CLEAR_STATUS_REG, MCI_STATUS_CMD_ERROR);\r
-\r
- if ((Status & MCI_STATUS_CMD_START_BIT_ERROR)) {\r
- DEBUG ((EFI_D_ERROR, "MciSendCommand(CmdIndex:%d) Start bit Error! Response:0x%X Status:0x%x\n", (Cmd & 0x3F), MmioRead32 (MCI_RESPONSE0_REG), Status));\r
- RetVal = EFI_NO_RESPONSE;\r
- } else if ((Status & MCI_STATUS_CMD_CMDTIMEOUT)) {\r
- //DEBUG ((EFI_D_ERROR, "MciSendCommand(CmdIndex:%d) TIMEOUT! Response:0x%X Status:0x%x\n", (Cmd & 0x3F), MmioRead32 (MCI_RESPONSE0_REG), Status));\r
- RetVal = EFI_TIMEOUT;\r
- } else if ((!(MmcCmd & MMC_CMD_NO_CRC_RESPONSE)) && (Status & MCI_STATUS_CMD_CMDCRCFAIL)) {\r
- // The CMD1 and response type R3 do not contain CRC. We should ignore the CRC failed Status.\r
- RetVal = EFI_CRC_ERROR;\r
- }\r
- }\r
-\r
- // Disable Command Path\r
- CmdCtrlReg = MmioRead32 (MCI_COMMAND_REG);\r
- MmioWrite32 (MCI_COMMAND_REG, (CmdCtrlReg & ~MCI_CPSM_ENABLE));\r
- return RetVal;\r
-}\r
-\r
-EFI_STATUS\r
-MciReceiveResponse (\r
- IN EFI_MMC_HOST_PROTOCOL *This,\r
- IN MMC_RESPONSE_TYPE Type,\r
- IN UINT32* Buffer\r
- )\r
-{\r
- if (Buffer == NULL) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- if ( (Type == MMC_RESPONSE_TYPE_R1)\r
- || (Type == MMC_RESPONSE_TYPE_R1b)\r
- || (Type == MMC_RESPONSE_TYPE_R3)\r
- || (Type == MMC_RESPONSE_TYPE_R6)\r
- || (Type == MMC_RESPONSE_TYPE_R7))\r
- {\r
- Buffer[0] = MmioRead32 (MCI_RESPONSE3_REG);\r
- } else if (Type == MMC_RESPONSE_TYPE_R2) {\r
- Buffer[0] = MmioRead32 (MCI_RESPONSE0_REG);\r
- Buffer[1] = MmioRead32 (MCI_RESPONSE1_REG);\r
- Buffer[2] = MmioRead32 (MCI_RESPONSE2_REG);\r
- Buffer[3] = MmioRead32 (MCI_RESPONSE3_REG);\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-EFI_STATUS\r
-MciReadBlockData (\r
- IN EFI_MMC_HOST_PROTOCOL *This,\r
- IN EFI_LBA Lba,\r
- IN UINTN Length,\r
- IN UINT32* Buffer\r
- )\r
-{\r
- UINTN Loop;\r
- UINTN Finish;\r
- UINTN Status;\r
- EFI_STATUS RetVal;\r
- UINTN DataCtrlReg;\r
- EFI_TPL Tpl;\r
-\r
- RetVal = EFI_SUCCESS;\r
-\r
- // Read data from the RX FIFO\r
- Loop = 0;\r
- if (Length < MMCI0_BLOCKLEN) {\r
- Finish = Length / 4;\r
- } else {\r
- Finish = MMCI0_BLOCKLEN / 4;\r
- }\r
-\r
- // Raise the TPL at the highest level to disable Interrupts.\r
- Tpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);\r
-\r
- do {\r
- // Read the Status flags\r
- Status = MmioRead32 (MCI_STATUS_REG);\r
-\r
- // Do eight reads if possible else a single read\r
- if (Status & MCI_STATUS_CMD_RXFIFOHALFFULL) {\r
- Buffer[Loop] = MmioRead32(MCI_FIFO_REG);\r
- Loop++;\r
- Buffer[Loop] = MmioRead32(MCI_FIFO_REG);\r
- Loop++;\r
- Buffer[Loop] = MmioRead32(MCI_FIFO_REG);\r
- Loop++;\r
- Buffer[Loop] = MmioRead32(MCI_FIFO_REG);\r
- Loop++;\r
- Buffer[Loop] = MmioRead32(MCI_FIFO_REG);\r
- Loop++;\r
- Buffer[Loop] = MmioRead32(MCI_FIFO_REG);\r
- Loop++;\r
- Buffer[Loop] = MmioRead32(MCI_FIFO_REG);\r
- Loop++;\r
- Buffer[Loop] = MmioRead32(MCI_FIFO_REG);\r
- Loop++;\r
- } else if (Status & MCI_STATUS_CMD_RXDATAAVAILBL) {\r
- Buffer[Loop] = MmioRead32(MCI_FIFO_REG);\r
- Loop++;\r
- } else {\r
- //Check for error conditions and timeouts\r
- if (Status & MCI_STATUS_CMD_DATATIMEOUT) {\r
- DEBUG ((EFI_D_ERROR, "MciReadBlockData(): TIMEOUT! Response:0x%X Status:0x%x\n", MmioRead32 (MCI_RESPONSE0_REG), Status));\r
- RetVal = EFI_TIMEOUT;\r
- break;\r
- } else if (Status & MCI_STATUS_CMD_DATACRCFAIL) {\r
- DEBUG ((EFI_D_ERROR, "MciReadBlockData(): CRC Error! Response:0x%X Status:0x%x\n", MmioRead32 (MCI_RESPONSE0_REG), Status));\r
- RetVal = EFI_CRC_ERROR;\r
- break;\r
- } else if (Status & MCI_STATUS_CMD_START_BIT_ERROR) {\r
- DEBUG ((EFI_D_ERROR, "MciReadBlockData(): Start-bit Error! Response:0x%X Status:0x%x\n", MmioRead32 (MCI_RESPONSE0_REG), Status));\r
- RetVal = EFI_NO_RESPONSE;\r
- break;\r
- }\r
- }\r
- //clear RX over run flag\r
- if(Status & MCI_STATUS_CMD_RXOVERRUN) {\r
- MmioWrite32(MCI_CLEAR_STATUS_REG, MCI_STATUS_CMD_RXOVERRUN);\r
- }\r
- } while ((Loop < Finish));\r
-\r
- // Restore Tpl\r
- gBS->RestoreTPL (Tpl);\r
-\r
- // Clear Status flags\r
- MmioWrite32 (MCI_CLEAR_STATUS_REG, MCI_CLR_ALL_STATUS);\r
-\r
- //Disable Data path\r
- DataCtrlReg = MmioRead32 (MCI_DATA_CTL_REG);\r
- MmioWrite32 (MCI_DATA_CTL_REG, (DataCtrlReg & MCI_DATACTL_DISABLE_MASK));\r
-\r
- return RetVal;\r
-}\r
-\r
-EFI_STATUS\r
-MciWriteBlockData (\r
- IN EFI_MMC_HOST_PROTOCOL *This,\r
- IN EFI_LBA Lba,\r
- IN UINTN Length,\r
- IN UINT32* Buffer\r
- )\r
-{\r
- UINTN Loop;\r
- UINTN Finish;\r
- UINTN Timer;\r
- UINTN Status;\r
- EFI_STATUS RetVal;\r
- UINTN DataCtrlReg;\r
- EFI_TPL Tpl;\r
-\r
- RetVal = EFI_SUCCESS;\r
-\r
- // Write the data to the TX FIFO\r
- Loop = 0;\r
- Finish = MMCI0_BLOCKLEN / 4;\r
- Timer = MMCI0_TIMEOUT * 100;\r
-\r
- // Raise the TPL at the highest level to disable Interrupts.\r
- Tpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);\r
-\r
- do {\r
- // Read the Status flags\r
- Status = MmioRead32 (MCI_STATUS_REG);\r
-\r
- // Do eight writes if possible else a single write\r
- if (Status & MCI_STATUS_CMD_TXFIFOHALFEMPTY) {\r
- MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);\r
- Loop++;\r
- MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);\r
- Loop++;\r
- MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);\r
- Loop++;\r
- MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);\r
- Loop++;\r
- MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);\r
- Loop++;\r
- MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);\r
- Loop++;\r
- MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);\r
- Loop++;\r
- MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);\r
- Loop++;\r
- } else if (!(Status & MCI_STATUS_CMD_TXFIFOFULL)) {\r
- MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);\r
- Loop++;\r
- } else {\r
- // Check for error conditions and timeouts\r
- if (Status & MCI_STATUS_CMD_DATATIMEOUT) {\r
- DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): TIMEOUT! Response:0x%X Status:0x%x\n", MmioRead32 (MCI_RESPONSE0_REG), Status));\r
- RetVal = EFI_TIMEOUT;\r
- goto Exit;\r
- } else if (Status & MCI_STATUS_CMD_DATACRCFAIL) {\r
- DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): CRC Error! Response:0x%X Status:0x%x\n", MmioRead32 (MCI_RESPONSE0_REG), Status));\r
- RetVal = EFI_CRC_ERROR;\r
- goto Exit;\r
- } else if (Status & MCI_STATUS_CMD_TX_UNDERRUN) {\r
- DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): TX buffer Underrun! Response:0x%X Status:0x%x, Number of bytes written 0x%x\n",MmioRead32(MCI_RESPONSE0_REG),Status, Loop));\r
- RetVal = EFI_BUFFER_TOO_SMALL;\r
- ASSERT(0);\r
- goto Exit;\r
- }\r
- }\r
- } while (Loop < Finish);\r
-\r
- // Restore Tpl\r
- gBS->RestoreTPL (Tpl);\r
-\r
- // Wait for FIFO to drain\r
- Timer = MMCI0_TIMEOUT * 60;\r
- Status = MmioRead32 (MCI_STATUS_REG);\r
-#ifndef USE_STREAM\r
- // Single block\r
- while (((Status & MCI_STATUS_TXDONE) != MCI_STATUS_TXDONE) && Timer) {\r
-#else\r
- // Stream\r
- while (((Status & MCI_STATUS_CMD_DATAEND) != MCI_STATUS_CMD_DATAEND) && Timer) {\r
-#endif\r
- NanoSecondDelay(10);\r
- Status = MmioRead32 (MCI_STATUS_REG);\r
- Timer--;\r
- }\r
-\r
- // Clear Status flags\r
- MmioWrite32 (MCI_CLEAR_STATUS_REG, MCI_CLR_ALL_STATUS);\r
-\r
- if (Timer == 0) {\r
- DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): Data End timeout Number of words written 0x%x\n", Loop));\r
- RetVal = EFI_TIMEOUT;\r
- }\r
-\r
-Exit:\r
- // Disable Data path\r
- DataCtrlReg = MmioRead32 (MCI_DATA_CTL_REG);\r
- MmioWrite32 (MCI_DATA_CTL_REG, (DataCtrlReg & MCI_DATACTL_DISABLE_MASK));\r
- return RetVal;\r
-}\r
-\r
-EFI_STATUS\r
-MciNotifyState (\r
- IN EFI_MMC_HOST_PROTOCOL *This,\r
- IN MMC_STATE State\r
- )\r
-{\r
- UINT32 Data32;\r
-\r
- switch (State) {\r
- case MmcInvalidState:\r
- ASSERT (0);\r
- break;\r
- case MmcHwInitializationState:\r
- // If device already turn on then restart it\r
- Data32 = MmioRead32 (MCI_POWER_CONTROL_REG);\r
- if ((Data32 & 0x2) == MCI_POWER_UP) {\r
- MCI_TRACE ("MciNotifyState(MmcHwInitializationState): TurnOff MCI");\r
-\r
- // Turn off\r
- MmioWrite32 (MCI_CLOCK_CONTROL_REG, 0);\r
- MmioWrite32 (MCI_POWER_CONTROL_REG, 0);\r
- MicroSecondDelay (100);\r
- }\r
-\r
- MCI_TRACE ("MciNotifyState(MmcHwInitializationState): TurnOn MCI");\r
- // Setup clock\r
- // - 0x1D = 29 => should be the clock divider to be less than 400kHz at MCLK = 24Mhz\r
- MmioWrite32 (MCI_CLOCK_CONTROL_REG, 0x1D | MCI_CLOCK_ENABLE | MCI_CLOCK_POWERSAVE);\r
-\r
- // Set the voltage\r
- MmioWrite32 (MCI_POWER_CONTROL_REG, MCI_POWER_OPENDRAIN | (15<<2));\r
- MmioWrite32 (MCI_POWER_CONTROL_REG, MCI_POWER_ROD | MCI_POWER_OPENDRAIN | (15<<2) | MCI_POWER_UP);\r
- MicroSecondDelay (10);\r
- MmioWrite32 (MCI_POWER_CONTROL_REG, MCI_POWER_ROD | MCI_POWER_OPENDRAIN | (15<<2) | MCI_POWER_ON);\r
- MicroSecondDelay (100);\r
-\r
- // Set Data Length & Data Timer\r
- MmioWrite32 (MCI_DATA_TIMER_REG, 0xFFFFF);\r
- MmioWrite32 (MCI_DATA_LENGTH_REG, 8);\r
-\r
- ASSERT ((MmioRead32 (MCI_POWER_CONTROL_REG) & 0x3) == MCI_POWER_ON);\r
- break;\r
- case MmcIdleState:\r
- MCI_TRACE ("MciNotifyState(MmcIdleState)");\r
- break;\r
- case MmcReadyState:\r
- MCI_TRACE ("MciNotifyState(MmcReadyState)");\r
- break;\r
- case MmcIdentificationState:\r
- MCI_TRACE ("MciNotifyState (MmcIdentificationState)");\r
- break;\r
- case MmcStandByState:{\r
- volatile UINT32 PwrCtrlReg;\r
- MCI_TRACE ("MciNotifyState (MmcStandByState)");\r
-\r
- // Enable MCICMD push-pull drive\r
- PwrCtrlReg = MmioRead32 (MCI_POWER_CONTROL_REG);\r
- //Disable Open Drain output\r
- PwrCtrlReg &= ~ (MCI_POWER_OPENDRAIN);\r
- MmioWrite32 (MCI_POWER_CONTROL_REG, PwrCtrlReg);\r
-\r
- // Set MMCI0 clock to 4MHz (24MHz may be possible with cache enabled)\r
- //\r
- // Note: Increasing clock speed causes TX FIFO under-run errors.\r
- // So careful when optimising this driver for higher performance.\r
- //\r
- MmioWrite32(MCI_CLOCK_CONTROL_REG,0x02 | MCI_CLOCK_ENABLE | MCI_CLOCK_POWERSAVE);\r
- // Set MMCI0 clock to 24MHz (by bypassing the divider)\r
- //MmioWrite32(MCI_CLOCK_CONTROL_REG,MCI_CLOCK_BYPASS | MCI_CLOCK_ENABLE);\r
- break;\r
- }\r
- case MmcTransferState:\r
- //MCI_TRACE ("MciNotifyState(MmcTransferState)");\r
- break;\r
- case MmcSendingDataState:\r
- MCI_TRACE ("MciNotifyState(MmcSendingDataState)");\r
- break;\r
- case MmcReceiveDataState:\r
- MCI_TRACE ("MciNotifyState(MmcReceiveDataState)");\r
- break;\r
- case MmcProgrammingState:\r
- MCI_TRACE ("MciNotifyState(MmcProgrammingState)");\r
- break;\r
- case MmcDisconnectState:\r
- MCI_TRACE ("MciNotifyState(MmcDisconnectState)");\r
- break;\r
- default:\r
- ASSERT (0);\r
- }\r
- return EFI_SUCCESS;\r
-}\r
-\r
-EFI_GUID mPL180MciDevicePathGuid = EFI_CALLER_ID_GUID;\r
-\r
-EFI_STATUS\r
-MciBuildDevicePath (\r
- IN EFI_MMC_HOST_PROTOCOL *This,\r
- IN EFI_DEVICE_PATH_PROTOCOL **DevicePath\r
- )\r
-{\r
- EFI_DEVICE_PATH_PROTOCOL *NewDevicePathNode;\r
-\r
- NewDevicePathNode = CreateDeviceNode (HARDWARE_DEVICE_PATH, HW_VENDOR_DP, sizeof (VENDOR_DEVICE_PATH));\r
- CopyGuid (& ((VENDOR_DEVICE_PATH*)NewDevicePathNode)->Guid, &mPL180MciDevicePathGuid);\r
-\r
- *DevicePath = NewDevicePathNode;\r
- return EFI_SUCCESS;\r
-}\r
-\r
-EFI_MMC_HOST_PROTOCOL gMciHost = {\r
- MMC_HOST_PROTOCOL_REVISION,\r
- MciIsCardPresent,\r
- MciIsReadOnly,\r
- MciBuildDevicePath,\r
- MciNotifyState,\r
- MciSendCommand,\r
- MciReceiveResponse,\r
- MciReadBlockData,\r
- MciWriteBlockData\r
-};\r
-\r
-EFI_STATUS\r
-PL180MciDxeInitialize (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
- )\r
-{\r
- EFI_STATUS Status;\r
- EFI_HANDLE Handle;\r
-\r
- DEBUG ((EFI_D_WARN, "Probing ID registers at 0x%lx for a PL180\n",\r
- MCI_PERIPH_ID_REG0));\r
-\r
- // Check if this is a PL180\r
- if (MmioRead8 (MCI_PERIPH_ID_REG0) != MCI_PERIPH_ID0 ||\r
- MmioRead8 (MCI_PERIPH_ID_REG1) != MCI_PERIPH_ID1 ||\r
- MmioRead8 (MCI_PERIPH_ID_REG2) != MCI_PERIPH_ID2 ||\r
- MmioRead8 (MCI_PCELL_ID_REG0) != MCI_PCELL_ID0 ||\r
- MmioRead8 (MCI_PCELL_ID_REG1) != MCI_PCELL_ID1 ||\r
- MmioRead8 (MCI_PCELL_ID_REG2) != MCI_PCELL_ID2 ||\r
- MmioRead8 (MCI_PCELL_ID_REG3) != MCI_PCELL_ID3) {\r
-\r
- DEBUG ((EFI_D_WARN, "Probing ID registers at 0x%lx for a PL180"\r
- " failed\n", MCI_PERIPH_ID_REG0));\r
- return EFI_NOT_FOUND;\r
- }\r
-\r
- Handle = NULL;\r
-\r
- MCI_TRACE ("PL180MciDxeInitialize()");\r
-\r
- //Publish Component Name, BlockIO protocol interfaces\r
- Status = gBS->InstallMultipleProtocolInterfaces (\r
- &Handle,\r
- &gEmbeddedMmcHostProtocolGuid, &gMciHost,\r
- NULL\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- return EFI_SUCCESS;\r
-}\r
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