ArmPkg: Move ARM Platform drivers from ArmPkg/Drivers/ to ArmPlatformPkg/Drivers/

[mirror_edk2.git] / ArmPlatformPkg / Include / Drivers / PL031RealTimeClock.h

diff --git a/ArmPlatformPkg/Include/Drivers/PL031RealTimeClock.h b/ArmPlatformPkg/Include/Drivers/PL031RealTimeClock.h
index 8c26d6605348d0879581ab0d7d5949137887af32..4c559c0c952bbe75f39cc9be3b2ddfb6816635ac 100644 (file)
--- a/ArmPlatformPkg/Include/Drivers/PL031RealTimeClock.h
+++ b/ArmPlatformPkg/Include/Drivers/PL031RealTimeClock.h
@@ -16,26 +16,23 @@
 #ifndef __PL031_REAL_TIME_CLOCK_H__\r
 #define __PL031_REAL_TIME_CLOCK_H__\r
 \r
-#include <Base.h>\r
-#include <ArmPlatform.h>\r
-\r
 // PL031 Registers\r
-#define PL031_RTC_DR_DATA_REGISTER                      (PL031_RTC_BASE + 0x000)\r
-#define PL031_RTC_MR_MATCH_REGISTER                     (PL031_RTC_BASE + 0x004)\r
-#define PL031_RTC_LR_LOAD_REGISTER                      (PL031_RTC_BASE + 0x008)\r
-#define PL031_RTC_CR_CONTROL_REGISTER                   (PL031_RTC_BASE + 0x00C)\r
-#define PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER      (PL031_RTC_BASE + 0x010)\r
-#define PL031_RTC_RIS_RAW_IRQ_STATUS_REGISTER           (PL031_RTC_BASE + 0x014)\r
-#define PL031_RTC_MIS_MASKED_IRQ_STATUS_REGISTER        (PL031_RTC_BASE + 0x018)\r
-#define PL031_RTC_ICR_IRQ_CLEAR_REGISTER                (PL031_RTC_BASE + 0x01C)\r
-#define PL031_RTC_PERIPH_ID0                            (PL031_RTC_BASE + 0xFE0)\r
-#define PL031_RTC_PERIPH_ID1                            (PL031_RTC_BASE + 0xFE4)\r
-#define PL031_RTC_PERIPH_ID2                            (PL031_RTC_BASE + 0xFE8)\r
-#define PL031_RTC_PERIPH_ID3                            (PL031_RTC_BASE + 0xFEC)\r
-#define PL031_RTC_PCELL_ID0                             (PL031_RTC_BASE + 0xFF0)\r
-#define PL031_RTC_PCELL_ID1                             (PL031_RTC_BASE + 0xFF4)\r
-#define PL031_RTC_PCELL_ID2                             (PL031_RTC_BASE + 0xFF8)\r
-#define PL031_RTC_PCELL_ID3                             (PL031_RTC_BASE + 0xFFC)\r
+#define PL031_RTC_DR_DATA_REGISTER                      ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x000)\r
+#define PL031_RTC_MR_MATCH_REGISTER                     ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x004)\r
+#define PL031_RTC_LR_LOAD_REGISTER                      ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x008)\r
+#define PL031_RTC_CR_CONTROL_REGISTER                   ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x00C)\r
+#define PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER      ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x010)\r
+#define PL031_RTC_RIS_RAW_IRQ_STATUS_REGISTER           ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x014)\r
+#define PL031_RTC_MIS_MASKED_IRQ_STATUS_REGISTER        ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x018)\r
+#define PL031_RTC_ICR_IRQ_CLEAR_REGISTER                ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x01C)\r
+#define PL031_RTC_PERIPH_ID0                            ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFE0)\r
+#define PL031_RTC_PERIPH_ID1                            ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFE4)\r
+#define PL031_RTC_PERIPH_ID2                            ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFE8)\r
+#define PL031_RTC_PERIPH_ID3                            ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFEC)\r
+#define PL031_RTC_PCELL_ID0                             ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFF0)\r
+#define PL031_RTC_PCELL_ID1                             ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFF4)\r
+#define PL031_RTC_PCELL_ID2                             ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFF8)\r
+#define PL031_RTC_PCELL_ID3                             ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFFC)\r
 \r
 // PL031 Values\r
 #define PL031_RTC_ENABLED                               0x00000001\r