ArmPlatformPkg: remove unused SP804 driver and TimerLib implementation

[mirror_edk2.git] / ArmPlatformPkg / Include / Drivers / SP804Timer.h

diff --git a/ArmPlatformPkg/Include/Drivers/SP804Timer.h b/ArmPlatformPkg/Include/Drivers/SP804Timer.h
deleted file mode 100644 (file)
index 904b13c..0000000
--- a/ArmPlatformPkg/Include/Drivers/SP804Timer.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/** @file\r
-*\r
-*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
-*\r
-*  This program and the accompanying materials\r
-*  are licensed and made available under the terms and conditions of the BSD License\r
-*  which accompanies this distribution.  The full text of the license may be found at\r
-*  http://opensource.org/licenses/bsd-license.php\r
-*\r
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-\r
-#ifndef _SP804_TIMER_H__\r
-#define _SP804_TIMER_H__\r
-\r
-// SP804 Timer constants\r
-// Note: The SP804 Timer module comprises two timers, Timer_0 and Timer_1\r
-//       These timers are identical and all their registers have an offset of 0x20\r
-//       i.e. SP804_TIMER_0_LOAD_REG = 0x00 and SP804_TIMER_1_LOAD_REG = 0x20\r
-//       Therefore, define all registers only once and adjust the base addresses by 0x20\r
-#define SP804_TIMER_LOAD_REG            0x00\r
-#define SP804_TIMER_CURRENT_REG         0x04\r
-#define SP804_TIMER_CONTROL_REG         0x08\r
-#define SP804_TIMER_INT_CLR_REG         0x0C\r
-#define SP804_TIMER_RAW_INT_STS_REG     0x10\r
-#define SP804_TIMER_MSK_INT_STS_REG     0x14\r
-#define SP804_TIMER_BG_LOAD_REG         0x18\r
-\r
-// Timer control register bit definitions\r
-#define SP804_TIMER_CTRL_ONESHOT        BIT0\r
-#define SP804_TIMER_CTRL_32BIT          BIT1\r
-#define SP804_TIMER_CTRL_PRESCALE_MASK  (BIT3|BIT2)\r
-#define SP804_PRESCALE_DIV_1            0\r
-#define SP804_PRESCALE_DIV_16           BIT2\r
-#define SP804_PRESCALE_DIV_256          BIT3\r
-#define SP804_TIMER_CTRL_INT_ENABLE     BIT5\r
-#define SP804_TIMER_CTRL_PERIODIC       BIT6\r
-#define SP804_TIMER_CTRL_ENABLE         BIT7\r
-\r
-// Other SP804 Timer definitions\r
-#define SP804_MAX_TICKS                 0xFFFFFFFF\r
-\r
-// SP810 System Controller constants\r
-#define SP810_SYS_CTRL_REG              0x00\r
-#define SP810_SYS_CTRL_TIMER0_TIMCLK    BIT15 // 0=REFCLK, 1=TIMCLK\r
-#define SP810_SYS_CTRL_TIMER0_EN        BIT16\r
-#define SP810_SYS_CTRL_TIMER1_TIMCLK    BIT17 // 0=REFCLK, 1=TIMCLK\r
-#define SP810_SYS_CTRL_TIMER1_EN        BIT18\r
-#define SP810_SYS_CTRL_TIMER2_TIMCLK    BIT19 // 0=REFCLK, 1=TIMCLK\r
-#define SP810_SYS_CTRL_TIMER2_EN        BIT20\r
-#define SP810_SYS_CTRL_TIMER3_TIMCLK    BIT21 // 0=REFCLK, 1=TIMCLK\r
-#define SP810_SYS_CTRL_TIMER3_EN        BIT22\r
-\r
-#endif\r