ArmPlatformPkg: Introduce Primary core macros

[mirror_edk2.git] / ArmPlatformPkg / Library / DebugSecExtraActionLib / DebugSecExtraActionLib.c

diff --git a/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c b/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c
index b9812142ed6013b23a56545fafbd53783ff81255..57390793f75d722cd053de4312ede53c05de6310 100755 (executable)
--- a/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c
+++ b/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c
@@ -14,14 +14,14 @@
 \r
 #include <PiPei.h>\r
 \r
+#include <Library/ArmLib.h>\r
 #include <Library/ArmGicLib.h>\r
 #include <Library/DebugLib.h>\r
 #include <Library/PcdLib.h>\r
 #include <Library/PrintLib.h>\r
 #include <Library/SerialPortLib.h>\r
-#include <Chipset/ArmV7.h>
 \r
-#define ARM_PRIMARY_CORE    0\r
+#include <Chipset/ArmV7.h>
 \r
 // When the firmware is built as not Standalone, the secondary cores need to wait the firmware\r
 // entirely written into DRAM. It is the firmware from DRAM which will wake up the secondary cores.\r
@@ -38,7 +38,7 @@ NonSecureWaitForFirmware (
   ArmCallWFI();\r
 \r
   // Acknowledge the interrupt and send End of Interrupt signal.\r
-  ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), ARM_PRIMARY_CORE);\r
+  ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);\r
 \r
   // Jump to secondary core entry point.\r
   secondary_start ();\r
@@ -56,7 +56,7 @@ NonSecureWaitForFirmware (
 **/\r
 VOID\r
 ArmPlatformSecExtraAction (\r
-  IN  UINTN         CoreId,\r
+  IN  UINTN         MpId,\r
   OUT UINTN*        JumpAddress\r
   )\r
 {\r
@@ -64,7 +64,7 @@ ArmPlatformSecExtraAction (
   UINTN           CharCount;\r
 \r
   if (FeaturePcdGet (PcdStandalone) == FALSE) {\r
-    if (CoreId == ARM_PRIMARY_CORE) {\r
+    if (IS_PRIMARY_CORE(MpId)) {\r
       UINTN*   StartAddress = (UINTN*)PcdGet32(PcdNormalFvBaseAddress);\r
 \r
       // Patch the DRAM to make an infinite loop at the start address\r
@@ -85,7 +85,7 @@ ArmPlatformSecExtraAction (
       *JumpAddress = (UINTN)NonSecureWaitForFirmware;\r
     }\r
   } else if (FeaturePcdGet (PcdSystemMemoryInitializeInSec)) {\r
-    if (CoreId == ARM_PRIMARY_CORE) {\r
+    if (IS_PRIMARY_CORE(MpId)) {\r
       // Signal the secondary cores they can jump to PEI phase\r
       ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
 \r