ArmPlatformPkg: Increase more ARM address Pcd entries to 64-bit.

[mirror_edk2.git] / ArmPlatformPkg / Library / DebugSecExtraActionLib / DebugSecExtraActionLib.c

diff --git a/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c b/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c
index 1e1b1ea64da987faef057d6a69a92f1c0c1a3217..a452e38751ee31803959f9e779a55459b1e2d3bf 100755 (executable)
--- a/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c
+++ b/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c
@@ -35,7 +35,7 @@ NonSecureWaitForFirmware (
   UINTN InterruptId;\r
 \r
   // The secondary cores will execute the firmware once wake from WFI.\r
-  SecondaryStart = (VOID (*)())PcdGet32 (PcdFvBaseAddress);\r
+  SecondaryStart = (VOID (*)())(UINTN)PcdGet64 (PcdFvBaseAddress);\r
 \r
   ArmCallWFI ();\r
 \r
@@ -69,6 +69,7 @@ ArmPlatformSecExtraAction (
 {\r
   CHAR8           Buffer[100];\r
   UINTN           CharCount;\r
+  UINTN*          StartAddress;\r
 \r
   if (FeaturePcdGet (PcdStandalone) == FALSE) {\r
 \r
@@ -77,7 +78,7 @@ ArmPlatformSecExtraAction (
     //\r
 \r
     if (ArmPlatformIsPrimaryCore (MpId)) {\r
-      UINTN*   StartAddress = (UINTN*)PcdGet32(PcdFvBaseAddress);\r
+      StartAddress = (UINTN*)(UINTN)PcdGet64 (PcdFvBaseAddress);\r
 \r
       // Patch the DRAM to make an infinite loop at the start address\r
       *StartAddress = 0xEAFFFFFE; // opcode for while(1)\r
@@ -85,7 +86,7 @@ ArmPlatformSecExtraAction (
       CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Waiting for firmware at 0x%08X ...\n\r",StartAddress);\r
       SerialPortWrite ((UINT8 *) Buffer, CharCount);\r
 \r
-      *JumpAddress = PcdGet32(PcdFvBaseAddress);\r
+      *JumpAddress = PcdGet64 (PcdFvBaseAddress);\r
     } else {\r
       // When the primary core is stopped by the hardware debugger to copy the firmware\r
       // into DRAM. The secondary cores are still running. As soon as the first bytes of\r
@@ -104,10 +105,10 @@ ArmPlatformSecExtraAction (
 \r
     if (ArmPlatformIsPrimaryCore (MpId)) {\r
       // Signal the secondary cores they can jump to PEI phase\r
-      ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));\r
+      ArmGicSendSgiTo (PcdGet32 (PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));\r
 \r
       // To enter into Non Secure state, we need to make a return from exception\r
-      *JumpAddress = PcdGet32(PcdFvBaseAddress);\r
+      *JumpAddress = PcdGet64 (PcdFvBaseAddress);\r
     } else {\r
       // We wait for the primary core to finish to initialize the System Memory. Otherwise the secondary\r
       // cores would make crash the system by setting their stacks in DRAM before the primary core has not\r
@@ -115,6 +116,6 @@ ArmPlatformSecExtraAction (
       *JumpAddress = (UINTN)NonSecureWaitForFirmware;\r
     }\r
   } else {\r
-    *JumpAddress = PcdGet32(PcdFvBaseAddress);\r
+    *JumpAddress = PcdGet64 (PcdFvBaseAddress);\r
   }\r
 }\r