/** @file\r
PEI Services Table Pointer Library.\r
- \r
+\r
This library is used for PEIM which does executed from flash device directly but\r
executed in memory.\r
\r
#include <Library/PcdLib.h>\r
\r
/**\r
- Caches a pointer PEI Services Table. \r
- \r
- Caches the pointer to the PEI Services Table specified by PeiServicesTablePointer \r
+ Caches a pointer PEI Services Table.\r
+\r
+ Caches the pointer to the PEI Services Table specified by PeiServicesTablePointer\r
in a platform specific manner.\r
- \r
+\r
If PeiServicesTablePointer is NULL, then ASSERT().\r
- \r
+\r
@param PeiServicesTablePointer The address of PeiServices pointer.\r
**/\r
VOID\r
/**\r
Retrieves the cached value of the PEI Services Table pointer.\r
\r
- Returns the cached value of the PEI Services Table pointer in a CPU specific manner \r
- as specified in the CPU binding section of the Platform Initialization Pre-EFI \r
+ Returns the cached value of the PEI Services Table pointer in a CPU specific manner\r
+ as specified in the CPU binding section of the Platform Initialization Pre-EFI\r
Initialization Core Interface Specification.\r
- \r
+\r
If the cached PEI Services Table pointer is NULL, then ASSERT().\r
\r
@return The pointer to PeiServices.\r
}\r
\r
/**\r
- Perform CPU specific actions required to migrate the PEI Services Table \r
+ Perform CPU specific actions required to migrate the PEI Services Table\r
pointer from temporary RAM to permanent RAM.\r
\r
- For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes \r
+ For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes\r
immediately preceding the Interrupt Descriptor Table (IDT) in memory.\r
- For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes \r
+ For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes\r
immediately preceding the Interrupt Descriptor Table (IDT) in memory.\r
For Itanium and ARM CPUs, a the PEI Services Table Pointer is stored in\r
- a dedicated CPU register. This means that there is no memory storage \r
- associated with storing the PEI Services Table pointer, so no additional \r
+ a dedicated CPU register. This means that there is no memory storage\r
+ associated with storing the PEI Services Table pointer, so no additional\r
migration actions are required for Itanium or ARM CPUs.\r
\r
**/\r