//\r
-// Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+// Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
//\r
\r
#include <AsmMacroIoLibV8.h>\r
-#include <Base.h>\r
-#include <Library/PcdLib.h>\r
-#include <AutoGen.h>\r
\r
-.text\r
-.align 3\r
-\r
-GCC_ASM_IMPORT(CEntryPoint)\r
-GCC_ASM_IMPORT(ArmPlatformGetCorePosition)\r
-GCC_ASM_IMPORT(ArmPlatformIsPrimaryCore)\r
-GCC_ASM_IMPORT(ArmReadMpidr)\r
-GCC_ASM_IMPORT(ArmPlatformPeiBootAction)\r
-GCC_ASM_EXPORT(_ModuleEntryPoint)\r
-\r
-StartupAddr: .dword CEntryPoint\r
-\r
-ASM_PFX(_ModuleEntryPoint):\r
+ASM_FUNC(_ModuleEntryPoint)\r
// Do early platform specific actions\r
bl ASM_PFX(ArmPlatformPeiBootAction)\r
\r
// changes.\r
\r
// Which EL are we running at? Every EL needs some level of setup...\r
- EL1_OR_EL2_OR_EL3(x0)\r
+// We should not run this code in EL3\r
+ EL1_OR_EL2(x0)\r
1:bl ASM_PFX(SetupExceptionLevel1)\r
b ASM_PFX(MainEntryPoint)\r
2:bl ASM_PFX(SetupExceptionLevel2)\r
b ASM_PFX(MainEntryPoint)\r
-3:// If we are at EL3 we die.\r
- b dead\r
\r
ASM_PFX(MainEntryPoint):\r
// Identify CPU ID\r
bl ASM_PFX(ArmPlatformIsPrimaryCore)\r
\r
// Get the top of the primary stacks (and the base of the secondary stacks)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoresStackBase), x1)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), x2)\r
- add x1, x1, x2\r
+ MOV64 (x1, FixedPcdGet64(PcdCPUCoresStackBase) + FixedPcdGet32(PcdCPUCorePrimaryStackSize))\r
\r
// x0 is equal to 1 if I am the primary core\r
cmp x0, #1\r
add x0, x0, #1\r
\r
// StackOffset = CorePos * StackSize\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), x2)\r
+ MOV32 (x2, FixedPcdGet32(PcdCPUCoreSecondaryStackSize))\r
mul x0, x0, x2\r
// SP = StackBase + StackOffset\r
add sp, x6, x0\r
\r
_PrepareArguments:\r
// The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector\r
- LoadConstantToReg (FixedPcdGet64(PcdFvBaseAddress), x2)\r
- add x2, x2, #8\r
- ldr x1, [x2]\r
+ MOV64 (x2, FixedPcdGet64(PcdFvBaseAddress))\r
+ ldr x1, [x2, #8]\r
\r
// Move sec startup address into a data register\r
// Ensure we're jumping to FV version of the code (not boot remapped alias)\r
- ldr x3, StartupAddr\r
+ ldr x3, =ASM_PFX(CEntryPoint)\r
+\r
+ // Set the frame pointer to NULL so any backtraces terminate here\r
+ mov x29, xzr\r
\r
// Jump to PrePeiCore C code\r
// x0 = mp_id\r
blr x3\r
\r
_SetupPrimaryCoreStack:\r
- // x1 contains the top of the primary stack\r
- LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), x2)\r
-\r
- // The reserved space for global variable must be 16-bytes aligned for pushing\r
- // 128-bit variable on the stack\r
- SetPrimaryStack (x1, x2, x3, x4)\r
+ mov sp, x1\r
+ MOV64 (x8, FixedPcdGet64 (PcdCPUCoresStackBase))\r
+ MOV64 (x9, FixedPcdGet32 (PcdInitValueInTempStack) |\\r
+ FixedPcdGet32 (PcdInitValueInTempStack) << 32)\r
+0:stp x9, x9, [x8], #16\r
+ cmp x8, x1\r
+ b.lt 0b\r
b _PrepareArguments\r
-\r
-dead:\r
- b dead\r