ArmPlatformPkg: Code cleaning

[mirror_edk2.git] / ArmPlatformPkg / PrePeiCore / MainMPCore.c

diff --git a/ArmPlatformPkg/PrePeiCore/MainMPCore.c b/ArmPlatformPkg/PrePeiCore/MainMPCore.c
index 2e6477d550c1b5731e6379141843bf4ec3b4ab3c..39de31a42aaa74829ee0258a3970f307be8afbc1 100644 (file)
--- a/ArmPlatformPkg/PrePeiCore/MainMPCore.c
+++ b/ArmPlatformPkg/PrePeiCore/MainMPCore.c
@@ -12,13 +12,14 @@
 *\r
 **/\r
 \r
-#include <PiPei.h>\r
 #include <Library/DebugLib.h>\r
 #include <Library/PcdLib.h>\r
 #include <Library/ArmMPCoreMailBoxLib.h>\r
 #include <Chipset/ArmV7.h>\r
 #include <Drivers/PL390Gic.h>\r
 \r
+#include "PrePeiCore.h"\r
+\r
 extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable;\r
 \r
 /*\r
@@ -32,60 +33,64 @@ extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable;
  */\r
 VOID\r
 EFIAPI\r
-secondary_main(IN UINTN CoreId)\r
+SecondaryMain (\r
+  IN UINTN CoreId\r
+  )\r
 {\r
-       //Function pointer to Secondary Core entry point\r
-       VOID (*secondary_start)(VOID);\r
-       UINTN secondary_entry_addr=0;\r
+  // Function pointer to Secondary Core entry point\r
+  VOID (*secondary_start)(VOID);\r
+  UINTN secondary_entry_addr=0;\r
 \r
-       //Clear Secondary cores MailBox\r
-       ArmClearMPCoreMailbox();\r
+  // Clear Secondary cores MailBox\r
+  ArmClearMPCoreMailbox();\r
 \r
-       while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {\r
-               ArmCallWFI();\r
-         //Acknowledge the interrupt and send End of Interrupt signal.\r
-               PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);\r
-       }\r
+  while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {\r
+    ArmCallWFI();\r
+    // Acknowledge the interrupt and send End of Interrupt signal.\r
+    PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);\r
+  }\r
 \r
-       secondary_start = (VOID (*)())secondary_entry_addr;\r
+  secondary_start = (VOID (*)())secondary_entry_addr;\r
 \r
-       //Jump to secondary core entry point.\r
-       secondary_start();\r
+  // Jump to secondary core entry point.\r
+  secondary_start();\r
 \r
-       //the secondaries shouldn't reach here\r
-       ASSERT(FALSE);\r
+  // The secondaries shouldn't reach here\r
+  ASSERT(FALSE);\r
 }\r
 \r
-VOID primary_main (\r
+VOID\r
+EFIAPI\r
+PrimaryMain (\r
   IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint\r
   )\r
 {\r
-       EFI_SEC_PEI_HAND_OFF        SecCoreData;\r
+  EFI_SEC_PEI_HAND_OFF        SecCoreData;\r
 \r
-       //Enable the GIC Distributor\r
-       PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r
+  //Enable the GIC Distributor\r
+  PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r
 \r
-       // If ArmVe has not been built as Standalone then we need to wake up the secondary cores\r
-       if (FeaturePcdGet(PcdStandalone) == FALSE) {\r
-               // Sending SGI to all the Secondary CPU interfaces\r
-               PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
-       }\r
+  // If ArmVe has not been built as Standalone then we need to wake up the secondary cores\r
+  if (FeaturePcdGet(PcdStandalone) == FALSE) {\r
+    // Sending SGI to all the Secondary CPU interfaces\r
+    PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
+  }\r
 \r
-       //\r
-       // Bind this information into the SEC hand-off state\r
-       // Note: this must be in sync with the stuff in the asm file\r
-       // Note also:  HOBs (pei temp ram) MUST be above stack\r
-       //\r
-       SecCoreData.DataSize               = sizeof(EFI_SEC_PEI_HAND_OFF);\r
-    SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress);\r
-    SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize);\r
-       SecCoreData.TemporaryRamBase       = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack)\r
-       SecCoreData.TemporaryRamSize       = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize);\r
-       SecCoreData.PeiTemporaryRamBase    = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));\r
-       SecCoreData.PeiTemporaryRamSize    = SecCoreData.TemporaryRamSize / 2;\r
-       SecCoreData.StackBase              = SecCoreData.TemporaryRamBase;\r
-       SecCoreData.StackSize              = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;\r
+  //\r
+  // Bind this information into the SEC hand-off state\r
+  // Note: this must be in sync with the stuff in the asm file\r
+  // Note also:  HOBs (pei temp ram) MUST be above stack\r
+  //\r
+  SecCoreData.DataSize               = sizeof(EFI_SEC_PEI_HAND_OFF);\r
+  SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress);\r
+  SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize);\r
+  SecCoreData.TemporaryRamBase       = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack)\r
+  SecCoreData.TemporaryRamSize       = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize);\r
+  SecCoreData.PeiTemporaryRamBase    = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));\r
+  SecCoreData.PeiTemporaryRamSize    = SecCoreData.TemporaryRamSize / 2;\r
+  SecCoreData.StackBase              = SecCoreData.TemporaryRamBase;\r
+  SecCoreData.StackSize              = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;\r
 \r
-       // jump to pei core entry point\r
-       (PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable);\r
+  // Jump to PEI core entry point\r
+  (PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable);\r
 }\r