BaseTools/Capsule: Do not support -o with --dump-info

[mirror_edk2.git] / ArmPlatformPkg / PrePeiCore / MainMPCore.c

diff --git a/ArmPlatformPkg/PrePeiCore/MainMPCore.c b/ArmPlatformPkg/PrePeiCore/MainMPCore.c
index 9547c1dd6585d00673bf7bb1524b346f2e234450..dc47adbaffc93fd20dfbee9e92563ecf53c59d83 100644 (file)
--- a/ArmPlatformPkg/PrePeiCore/MainMPCore.c
+++ b/ArmPlatformPkg/PrePeiCore/MainMPCore.c
@@ -1,6 +1,6 @@
 /** @file\r
 *\r
-*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
+*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
 *\r
 *  This program and the accompanying materials\r
 *  are licensed and made available under the terms and conditions of the BSD License\r
@@ -16,8 +16,6 @@
 \r
 #include <Ppi/ArmMpCoreInfo.h>\r
 \r
-#include <Chipset/ArmV7.h>\r
-\r
 #include "PrePeiCore.h"\r
 \r
 /*\r
@@ -47,6 +45,8 @@ SecondaryMain (
   UINT32                  CoreId;\r
   VOID                    (*SecondaryStart)(VOID);\r
   UINTN                   SecondaryEntryAddr;\r
+  UINTN                   AcknowledgeInterrupt;\r
+  UINTN                   InterruptId;\r
 \r
   ClusterId = GET_CLUSTER_ID(MpId);\r
   CoreId    = GET_CORE_ID(MpId);\r
@@ -82,12 +82,20 @@ SecondaryMain (
   // Clear Secondary cores MailBox\r
   MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);\r
 \r
-  SecondaryEntryAddr = 0;\r
-  while (SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress), SecondaryEntryAddr == 0) {\r
+  do {\r
     ArmCallWFI ();\r
+\r
+    // Read the Mailbox\r
+    SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);\r
+\r
     // Acknowledge the interrupt and send End of Interrupt signal.\r
-    ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);\r
-  }\r
+    AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), &InterruptId);\r
+    // Check if it is a valid interrupt ID\r
+    if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet64 (PcdGicDistributorBase))) {\r
+      // Got a valid SGI number hence signal End of Interrupt\r
+      ArmGicEndOfInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt);\r
+    }\r
+  } while (SecondaryEntryAddr == 0);\r
 \r
   // Jump to secondary core entry point.\r
   SecondaryStart = (VOID (*)())SecondaryEntryAddr;\r
@@ -112,18 +120,18 @@ PrimaryMain (
   CreatePpiList (&PpiListSize, &PpiList);\r
 \r
   // Enable the GIC Distributor\r
-  ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r
+  ArmGicEnableDistributor (PcdGet64(PcdGicDistributorBase));\r
 \r
   // If ArmVe has not been built as Standalone then we need to wake up the secondary cores\r
   if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {\r
     // Sending SGI to all the Secondary CPU interfaces\r
-    ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
+    ArmGicSendSgiTo (PcdGet64(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));\r
   }\r
 \r
   // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at\r
   // the base of the primary core stack\r
-  PpiListSize = ALIGN_VALUE(PpiListSize, 0x4);\r
-  TemporaryRamBase = (UINTN)PcdGet32 (PcdCPUCoresStackBase) + PpiListSize;\r
+  PpiListSize = ALIGN_VALUE(PpiListSize, CPU_STACK_ALIGNMENT);\r
+  TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;\r
   TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;\r
 \r
   //\r
@@ -132,15 +140,15 @@ PrimaryMain (
   // Note also:  HOBs (pei temp ram) MUST be above stack\r
   //\r
   SecCoreData.DataSize               = sizeof(EFI_SEC_PEI_HAND_OFF);\r
-  SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdFvBaseAddress);\r
+  SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress);\r
   SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);\r
   SecCoreData.TemporaryRamBase       = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)\r
   SecCoreData.TemporaryRamSize       = TemporaryRamSize;\r
   SecCoreData.PeiTemporaryRamBase    = SecCoreData.TemporaryRamBase;\r
-  SecCoreData.PeiTemporaryRamSize    = SecCoreData.TemporaryRamSize / 2;\r
-  SecCoreData.StackBase              = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize/2));\r
-  SecCoreData.StackSize              = SecCoreData.TemporaryRamSize / 2;\r
+  SecCoreData.PeiTemporaryRamSize    = ALIGN_VALUE (SecCoreData.TemporaryRamSize / 2, CPU_STACK_ALIGNMENT);\r
+  SecCoreData.StackBase              = (VOID *)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize);\r
+  SecCoreData.StackSize              = (TemporaryRamBase + TemporaryRamSize) - (UINTN)SecCoreData.StackBase;\r
 \r
   // Jump to PEI core entry point\r
-  (PeiCoreEntryPoint)(&SecCoreData, PpiList);\r
+  PeiCoreEntryPoint (&SecCoreData, PpiList);\r
 }\r