BaseTools/Capsule: Do not support -o with --dump-info

[mirror_edk2.git] / ArmPlatformPkg / PrePeiCore / MainMPCore.c

diff --git a/ArmPlatformPkg/PrePeiCore/MainMPCore.c b/ArmPlatformPkg/PrePeiCore/MainMPCore.c
index d40594f83508e4f997aaeafb4dcb077df69d5d47..dc47adbaffc93fd20dfbee9e92563ecf53c59d83 100644 (file)
--- a/ArmPlatformPkg/PrePeiCore/MainMPCore.c
+++ b/ArmPlatformPkg/PrePeiCore/MainMPCore.c
@@ -89,11 +89,11 @@ SecondaryMain (
     SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);\r
 \r
     // Acknowledge the interrupt and send End of Interrupt signal.\r
-    AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), &InterruptId);\r
+    AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), &InterruptId);\r
     // Check if it is a valid interrupt ID\r
-    if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet32 (PcdGicDistributorBase))) {\r
+    if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet64 (PcdGicDistributorBase))) {\r
       // Got a valid SGI number hence signal End of Interrupt\r
-      ArmGicEndOfInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt);\r
+      ArmGicEndOfInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt);\r
     }\r
   } while (SecondaryEntryAddr == 0);\r
 \r
@@ -120,37 +120,33 @@ PrimaryMain (
   CreatePpiList (&PpiListSize, &PpiList);\r
 \r
   // Enable the GIC Distributor\r
-  ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));\r
+  ArmGicEnableDistributor (PcdGet64(PcdGicDistributorBase));\r
 \r
   // If ArmVe has not been built as Standalone then we need to wake up the secondary cores\r
   if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {\r
     // Sending SGI to all the Secondary CPU interfaces\r
-    ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));\r
+    ArmGicSendSgiTo (PcdGet64(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));\r
   }\r
 \r
   // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at\r
   // the base of the primary core stack\r
-  PpiListSize = ALIGN_VALUE(PpiListSize, 0x4);\r
-  TemporaryRamBase = (UINTN)PcdGet32 (PcdCPUCoresStackBase) + PpiListSize;\r
+  PpiListSize = ALIGN_VALUE(PpiListSize, CPU_STACK_ALIGNMENT);\r
+  TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;\r
   TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;\r
 \r
-  // Make sure the size is 8-byte aligned. Once divided by 2, the size should be 4-byte aligned\r
-  // to ensure the stack pointer is 4-byte aligned.\r
-  TemporaryRamSize = TemporaryRamSize - (TemporaryRamSize & (0x8-1));\r
-\r
   //\r
   // Bind this information into the SEC hand-off state\r
   // Note: this must be in sync with the stuff in the asm file\r
   // Note also:  HOBs (pei temp ram) MUST be above stack\r
   //\r
   SecCoreData.DataSize               = sizeof(EFI_SEC_PEI_HAND_OFF);\r
-  SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdFvBaseAddress);\r
+  SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress);\r
   SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);\r
   SecCoreData.TemporaryRamBase       = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)\r
   SecCoreData.TemporaryRamSize       = TemporaryRamSize;\r
   SecCoreData.PeiTemporaryRamBase    = SecCoreData.TemporaryRamBase;\r
-  SecCoreData.PeiTemporaryRamSize    = SecCoreData.TemporaryRamSize / 2;\r
-  SecCoreData.StackBase              = (VOID *)ALIGN_VALUE((UINTN)(SecCoreData.TemporaryRamBase) + SecCoreData.PeiTemporaryRamSize, 0x4);\r
+  SecCoreData.PeiTemporaryRamSize    = ALIGN_VALUE (SecCoreData.TemporaryRamSize / 2, CPU_STACK_ALIGNMENT);\r
+  SecCoreData.StackBase              = (VOID *)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize);\r
   SecCoreData.StackSize              = (TemporaryRamBase + TemporaryRamSize) - (UINTN)SecCoreData.StackBase;\r
 \r
   // Jump to PEI core entry point\r