BaseTools/GenFw AARCH64: disregard ADRP instructions that are patched already

[mirror_edk2.git] / BaseTools / Source / C / GenFw / Elf64Convert.c

diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c
index d574300ac4fe315d4f2928db2c5f6428788bdfae..d623dce1f9da020f110de1dd14d1182e9f90818a 100644 (file)
--- a/BaseTools/Source/C/GenFw/Elf64Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
@@ -1044,6 +1044,19 @@ WriteSections64 (
             /* fall through */\r
 \r
           case R_AARCH64_ADR_PREL_PG_HI21:\r
+            //\r
+            // In order to handle Cortex-A53 erratum #843419, the LD linker may\r
+            // convert ADRP instructions into ADR instructions, but without\r
+            // updating the static relocation type, and so we may end up here\r
+            // while the instruction in question is actually ADR. So let's\r
+            // just disregard it: the section offset check we apply below to\r
+            // ADR instructions will trigger for its R_AARCH64_xxx_ABS_LO12_NC\r
+            // companion instruction as well, so it is safe to omit it here.\r
+            //\r
+            if ((*(UINT32 *)Targ & BIT31) == 0) {\r
+              break;\r
+            }\r
+\r
             //\r
             // AArch64 PG_H21 relocations are typically paired with ABS_LO12\r
             // relocations, where a PC-relative reference with +/- 4 GB range is\r