This library will parse the coreboot table in memory and extract those required\r
information.\r
\r
- Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/PcdLib.h>\r
+#include <Library/IoLib.h>\r
#include <Library/CbParseLib.h>\r
\r
#include <IndustryStandard/Acpi.h>\r
@return the UNIT64 value after convertion.\r
\r
**/\r
-UINT64 \r
+UINT64\r
cb_unpack64 (\r
IN struct cbuint64 val\r
)\r
\r
**/\r
VOID *\r
+EFIAPI\r
FindCbTag (\r
IN VOID *Start,\r
IN UINT32 Tag\r
\r
**/\r
RETURN_STATUS\r
+EFIAPI\r
FindCbMemTable (\r
IN struct cbmem_root *Root,\r
IN UINT32 TableId,\r
*pMemTableSize = Entries[Idx].size;\r
}\r
\r
- DEBUG ((EFI_D_INFO, "Find CbMemTable Id 0x%x, base %p, size 0x%x\n",
- TableId, *pMemTable, Entries[Idx].size));
+ DEBUG ((EFI_D_INFO, "Find CbMemTable Id 0x%x, base %p, size 0x%x\n",\r
+ TableId, *pMemTable, Entries[Idx].size));\r
return RETURN_SUCCESS;\r
}\r
}\r
/**\r
Acquire the memory information from the coreboot table in memory.\r
\r
- @param pLowMemorySize Pointer to the variable of low memory size\r
- @param pHighMemorySize Pointer to the variable of high memory size\r
+ @param MemInfoCallback The callback routine\r
+ @param pParam Pointer to the callback routine parameter\r
\r
@retval RETURN_SUCCESS Successfully find out the memory information.\r
- @retval RETURN_INVALID_PARAMETER Invalid input parameters.\r
@retval RETURN_NOT_FOUND Failed to find the memory information.\r
\r
**/\r
RETURN_STATUS\r
+EFIAPI\r
CbParseMemoryInfo (\r
- OUT UINT64 *pLowMemorySize,\r
- OUT UINT64 *pHighMemorySize\r
+ IN CB_MEM_INFO_CALLBACK MemInfoCallback,\r
+ IN VOID *pParam\r
)\r
{\r
struct cb_memory *rec;\r
UINT64 Size;\r
UINTN Index;\r
\r
- if ((pLowMemorySize == NULL) || (pHighMemorySize == NULL)) {\r
- return RETURN_INVALID_PARAMETER;\r
- }\r
-\r
//\r
// Get the coreboot memory table\r
//\r
return RETURN_NOT_FOUND;\r
}\r
\r
- *pLowMemorySize = 0;\r
- *pHighMemorySize = 0;\r
-\r
for (Index = 0; Index < MEM_RANGE_COUNT(rec); Index++) {\r
Range = MEM_RANGE_PTR(rec, Index);\r
Start = cb_unpack64(Range->start);\r
DEBUG ((EFI_D_INFO, "%d. %016lx - %016lx [%02x]\n",\r
Index, Start, Start + Size - 1, Range->type));\r
\r
- if (Range->type != CB_MEM_RAM) {\r
- continue;\r
- }\r
-\r
- if (Start + Size < 0x100000000ULL) {\r
- *pLowMemorySize = Start + Size;\r
- } else {\r
- *pHighMemorySize = Start + Size - 0x100000000ULL;\r
- }\r
+ MemInfoCallback (Start, Size, Range->type, pParam);\r
}\r
\r
- DEBUG ((EFI_D_INFO, "Low memory 0x%lx, High Memory 0x%lx\n", *pLowMemorySize, *pHighMemorySize));\r
-\r
return RETURN_SUCCESS;\r
}\r
\r
\r
**/\r
RETURN_STATUS\r
+EFIAPI\r
CbParseCbMemTable (\r
IN UINT32 TableId,\r
OUT VOID **pMemTable,\r
\r
**/\r
RETURN_STATUS\r
+EFIAPI\r
CbParseAcpiTable (\r
OUT VOID **pMemTable,\r
OUT UINT32 *pMemTableSize\r
\r
**/\r
RETURN_STATUS\r
+EFIAPI\r
CbParseSmbiosTable (\r
OUT VOID **pMemTable,\r
OUT UINT32 *pMemTableSize\r
\r
**/\r
RETURN_STATUS\r
+EFIAPI\r
CbParseFadtInfo (\r
OUT UINTN *pPmCtrlReg,\r
OUT UINTN *pPmTimerReg,\r
}\r
DEBUG ((EFI_D_INFO, "Reset Value 0x%x\n", Fadt->ResetValue));\r
\r
- if (pPmEvtReg != NULL) { \r
+ if (pPmEvtReg != NULL) {\r
*pPmEvtReg = Fadt->Pm1aEvtBlk;\r
DEBUG ((EFI_D_INFO, "PmEvt Reg 0x%x\n", Fadt->Pm1aEvtBlk));\r
}\r
\r
- if (pPmGpeEnReg != NULL) { \r
+ if (pPmGpeEnReg != NULL) {\r
*pPmGpeEnReg = Fadt->Gpe0Blk + Fadt->Gpe0BlkLen / 2;\r
DEBUG ((EFI_D_INFO, "PmGpeEn Reg 0x%x\n", *pPmGpeEnReg));\r
}\r
\r
- //
- // Verify values for proper operation
- //
- ASSERT(Fadt->Pm1aCntBlk != 0);
- ASSERT(Fadt->PmTmrBlk != 0);
- ASSERT(Fadt->ResetReg.Address != 0);
- ASSERT(Fadt->Pm1aEvtBlk != 0);
- ASSERT(Fadt->Gpe0Blk != 0);
-
+ //\r
+ // Verify values for proper operation\r
+ //\r
+ ASSERT(Fadt->Pm1aCntBlk != 0);\r
+ ASSERT(Fadt->PmTmrBlk != 0);\r
+ ASSERT(Fadt->ResetReg.Address != 0);\r
+ ASSERT(Fadt->Pm1aEvtBlk != 0);\r
+ ASSERT(Fadt->Gpe0Blk != 0);\r
+\r
+ DEBUG_CODE_BEGIN ();\r
+ BOOLEAN SciEnabled;\r
+\r
+ //\r
+ // Check the consistency of SCI enabling\r
+ //\r
+\r
+ //\r
+ // Get SCI_EN value\r
+ //\r
+ if (Fadt->Pm1CntLen == 4) {\r
+ SciEnabled = (IoRead32 (Fadt->Pm1aCntBlk) & BIT0)? TRUE : FALSE;\r
+ } else {\r
+ //\r
+ // if (Pm1CntLen == 2), use 16 bit IO read;\r
+ // if (Pm1CntLen != 2 && Pm1CntLen != 4), use 16 bit IO read as a fallback\r
+ //\r
+ SciEnabled = (IoRead16 (Fadt->Pm1aCntBlk) & BIT0)? TRUE : FALSE;\r
+ }\r
+\r
+ if (!(Fadt->Flags & EFI_ACPI_5_0_HW_REDUCED_ACPI) &&\r
+ (Fadt->SmiCmd == 0) &&\r
+ !SciEnabled) {\r
+ //\r
+ // The ACPI enabling status is inconsistent: SCI is not enabled but ACPI\r
+ // table does not provide a means to enable it through FADT->SmiCmd\r
+ //\r
+ DEBUG ((DEBUG_ERROR, "ERROR: The ACPI enabling status is inconsistent: SCI is not"\r
+ " enabled but the ACPI table does not provide a means to enable it through FADT->SmiCmd."\r
+ " This may cause issues in OS.\n"));\r
+ ASSERT (FALSE);\r
+ }\r
+ DEBUG_CODE_END ();\r
return RETURN_SUCCESS;\r
}\r
}\r
*pResetValue = Fadt->ResetValue;\r
DEBUG ((EFI_D_ERROR, "Reset Value 0x%x\n", Fadt->ResetValue));\r
\r
- if (pPmEvtReg != NULL) { \r
+ if (pPmEvtReg != NULL) {\r
*pPmEvtReg = Fadt->Pm1aEvtBlk;\r
DEBUG ((EFI_D_INFO, "PmEvt Reg 0x%x\n", Fadt->Pm1aEvtBlk));\r
}\r
\r
- if (pPmGpeEnReg != NULL) { \r
+ if (pPmGpeEnReg != NULL) {\r
*pPmGpeEnReg = Fadt->Gpe0Blk + Fadt->Gpe0BlkLen / 2;\r
DEBUG ((EFI_D_INFO, "PmGpeEn Reg 0x%x\n", *pPmGpeEnReg));\r
- } \r
+ }\r
return RETURN_SUCCESS;\r
}\r
}\r
\r
@param pRegBase Pointer to the base address of serial port registers\r
@param pRegAccessType Pointer to the access type of serial port registers\r
+ @param pRegWidth Pointer to the register width in bytes\r
@param pBaudrate Pointer to the serial port baudrate\r
+ @param pInputHertz Pointer to the input clock frequency\r
+ @param pUartPciAddr Pointer to the UART PCI bus, dev and func address\r
\r
@retval RETURN_SUCCESS Successfully find the serial port information.\r
@retval RETURN_NOT_FOUND Failed to find the serial port information .\r
\r
**/\r
RETURN_STATUS\r
+EFIAPI\r
CbParseSerialInfo (\r
OUT UINT32 *pRegBase,\r
OUT UINT32 *pRegAccessType,\r
- OUT UINT32 *pBaudrate\r
+ OUT UINT32 *pRegWidth,\r
+ OUT UINT32 *pBaudrate,\r
+ OUT UINT32 *pInputHertz,\r
+ OUT UINT32 *pUartPciAddr\r
)\r
{\r
struct cb_serial *CbSerial;\r
*pRegBase = CbSerial->baseaddr;\r
}\r
\r
+ if (pRegWidth != NULL) {\r
+ *pRegWidth = CbSerial->regwidth;\r
+ }\r
+\r
if (pRegAccessType != NULL) {\r
*pRegAccessType = CbSerial->type;\r
}\r
*pBaudrate = CbSerial->baud;\r
}\r
\r
+ if (pInputHertz != NULL) {\r
+ *pInputHertz = CbSerial->input_hertz;\r
+ }\r
+\r
+ if (pUartPciAddr != NULL) {\r
+ *pUartPciAddr = CbSerial->uart_pci_addr;\r
+ }\r
+\r
return RETURN_SUCCESS;\r
}\r
\r
\r
**/\r
RETURN_STATUS\r
+EFIAPI\r
CbParseGetCbHeader (\r
IN UINTN Level,\r
OUT VOID **HeaderPtr\r
\r
**/\r
RETURN_STATUS\r
+EFIAPI\r
CbParseFbInfo (\r
OUT FRAME_BUFFER_INFO *pFbInfo\r
)\r
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