+++ /dev/null
-/** @file\r
- Library instance of PciHostBridgeLib library class for coreboot.\r
-\r
- Copyright (C) 2016, Red Hat, Inc.\r
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
-\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
-**/\r
-#include <PiDxe.h>\r
-\r
-#include <IndustryStandard/Pci.h>\r
-#include <Protocol/PciHostBridgeResourceAllocation.h>\r
-#include <Protocol/PciRootBridgeIo.h>\r
-\r
-#include <Library/BaseMemoryLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/DevicePathLib.h>\r
-#include <Library/MemoryAllocationLib.h>\r
-#include <Library/PciHostBridgeLib.h>\r
-#include <Library/PciLib.h>\r
-\r
-#include "PciHostBridge.h"\r
-\r
-STATIC\r
-CONST\r
-CB_PCI_ROOT_BRIDGE_DEVICE_PATH mRootBridgeDevicePathTemplate = {\r
- {\r
- {\r
- ACPI_DEVICE_PATH,\r
- ACPI_DP,\r
- {\r
- (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),\r
- (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)\r
- }\r
- },\r
- EISA_PNP_ID(0x0A03), // HID\r
- 0 // UID\r
- },\r
-\r
- {\r
- END_DEVICE_PATH_TYPE,\r
- END_ENTIRE_DEVICE_PATH_SUBTYPE,\r
- {\r
- END_DEVICE_PATH_LENGTH,\r
- 0\r
- }\r
- }\r
-};\r
-\r
-\r
-/**\r
- Initialize a PCI_ROOT_BRIDGE structure.\r
-\r
- @param[in] Supports Supported attributes.\r
-\r
- @param[in] Attributes Initial attributes.\r
-\r
- @param[in] AllocAttributes Allocation attributes.\r
-\r
- @param[in] RootBusNumber The bus number to store in RootBus.\r
-\r
- @param[in] MaxSubBusNumber The inclusive maximum bus number that can be\r
- assigned to any subordinate bus found behind any\r
- PCI bridge hanging off this root bus.\r
-\r
- The caller is responsible for ensuring that\r
- RootBusNumber <= MaxSubBusNumber. If\r
- RootBusNumber equals MaxSubBusNumber, then the\r
- root bus has no room for subordinate buses.\r
-\r
- @param[in] Io IO aperture.\r
-\r
- @param[in] Mem MMIO aperture.\r
-\r
- @param[in] MemAbove4G MMIO aperture above 4G.\r
-\r
- @param[in] PMem Prefetchable MMIO aperture.\r
-\r
- @param[in] PMemAbove4G Prefetchable MMIO aperture above 4G.\r
-\r
- @param[out] RootBus The PCI_ROOT_BRIDGE structure (allocated by the\r
- caller) that should be filled in by this\r
- function.\r
-\r
- @retval EFI_SUCCESS Initialization successful. A device path\r
- consisting of an ACPI device path node, with\r
- UID = RootBusNumber, has been allocated and\r
- linked into RootBus.\r
-\r
- @retval EFI_OUT_OF_RESOURCES Memory allocation failed.\r
-**/\r
-EFI_STATUS\r
-InitRootBridge (\r
- IN UINT64 Supports,\r
- IN UINT64 Attributes,\r
- IN UINT64 AllocAttributes,\r
- IN UINT8 RootBusNumber,\r
- IN UINT8 MaxSubBusNumber,\r
- IN PCI_ROOT_BRIDGE_APERTURE *Io,\r
- IN PCI_ROOT_BRIDGE_APERTURE *Mem,\r
- IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,\r
- IN PCI_ROOT_BRIDGE_APERTURE *PMem,\r
- IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G,\r
- OUT PCI_ROOT_BRIDGE *RootBus\r
-)\r
-{\r
- CB_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath;\r
-\r
- //\r
- // Be safe if other fields are added to PCI_ROOT_BRIDGE later.\r
- //\r
- ZeroMem (RootBus, sizeof *RootBus);\r
-\r
- RootBus->Segment = 0;\r
-\r
- RootBus->Supports = Supports;\r
- RootBus->Attributes = Attributes;\r
-\r
- RootBus->DmaAbove4G = FALSE;\r
-\r
- RootBus->AllocationAttributes = AllocAttributes;\r
- RootBus->Bus.Base = RootBusNumber;\r
- RootBus->Bus.Limit = MaxSubBusNumber;\r
- CopyMem (&RootBus->Io, Io, sizeof (*Io));\r
- CopyMem (&RootBus->Mem, Mem, sizeof (*Mem));\r
- CopyMem (&RootBus->MemAbove4G, MemAbove4G, sizeof (*MemAbove4G));\r
- CopyMem (&RootBus->PMem, PMem, sizeof (*PMem));\r
- CopyMem (&RootBus->PMemAbove4G, PMemAbove4G, sizeof (*PMemAbove4G));\r
-\r
- RootBus->NoExtendedConfigSpace = FALSE;\r
-\r
- DevicePath = AllocateCopyPool (sizeof (mRootBridgeDevicePathTemplate),\r
- &mRootBridgeDevicePathTemplate);\r
- if (DevicePath == NULL) {\r
- DEBUG ((EFI_D_ERROR, "%a: %r\n", __FUNCTION__, EFI_OUT_OF_RESOURCES));\r
- return EFI_OUT_OF_RESOURCES;\r
- }\r
- DevicePath->AcpiDevicePath.UID = RootBusNumber;\r
- RootBus->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)DevicePath;\r
-\r
- DEBUG ((EFI_D_INFO,\r
- "%a: populated root bus %d, with room for %d subordinate bus(es)\n",\r
- __FUNCTION__, RootBusNumber, MaxSubBusNumber - RootBusNumber));\r
- return EFI_SUCCESS;\r
-}\r
-\r
-\r
-/**\r
- Return all the root bridge instances in an array.\r
-\r
- @param Count Return the count of root bridge instances.\r
-\r
- @return All the root bridge instances in an array.\r
- The array should be passed into PciHostBridgeFreeRootBridges()\r
- when it's not used.\r
-**/\r
-PCI_ROOT_BRIDGE *\r
-EFIAPI\r
-PciHostBridgeGetRootBridges (\r
- UINTN *Count\r
-)\r
-{\r
- return ScanForRootBridges (Count);\r
-}\r
-\r
-\r
-/**\r
- Free the root bridge instances array returned from\r
- PciHostBridgeGetRootBridges().\r
-\r
- @param The root bridge instances array.\r
- @param The count of the array.\r
-**/\r
-VOID\r
-EFIAPI\r
-PciHostBridgeFreeRootBridges (\r
- PCI_ROOT_BRIDGE *Bridges,\r
- UINTN Count\r
-)\r
-{\r
- if (Bridges == NULL && Count == 0) {\r
- return;\r
- }\r
- ASSERT (Bridges != NULL && Count > 0);\r
-\r
- do {\r
- --Count;\r
- FreePool (Bridges[Count].DevicePath);\r
- } while (Count > 0);\r
-\r
- FreePool (Bridges);\r
-}\r
-\r
-\r
-/**\r
- Inform the platform that the resource conflict happens.\r
-\r
- @param HostBridgeHandle Handle of the Host Bridge.\r
- @param Configuration Pointer to PCI I/O and PCI memory resource\r
- descriptors. The Configuration contains the resources\r
- for all the root bridges. The resource for each root\r
- bridge is terminated with END descriptor and an\r
- additional END is appended indicating the end of the\r
- entire resources. The resource descriptor field\r
- values follow the description in\r
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
- .SubmitResources().\r
-**/\r
-VOID\r
-EFIAPI\r
-PciHostBridgeResourceConflict (\r
- EFI_HANDLE HostBridgeHandle,\r
- VOID *Configuration\r
-)\r
-{\r
- //\r
- // coreboot UEFI Payload does not do PCI enumeration and should not call this\r
- // library interface.\r
- //\r
- ASSERT (FALSE);\r
-}\r
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