+++ /dev/null
-/** @file\r
- Basic Definition for IA32 Architecture.\r
- \r
-Copyright (c) 2006 - 2009, Intel Corporation\r
-All rights reserved. This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution. The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
-\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#ifndef _CPU_IA32_H_\r
-#define _CPU_IA32_H_\r
-\r
-typedef struct {\r
- UINT32 RegEax;\r
- UINT32 RegEbx;\r
- UINT32 RegEcx;\r
- UINT32 RegEdx;\r
-} EFI_CPUID_REGISTER;\r
-\r
-#pragma pack(1)\r
-//\r
-// Definition for IA32 microcode format\r
-//\r
-typedef struct {\r
- UINT32 HeaderVersion;\r
- UINT32 UpdateRevision;\r
- UINT32 Date;\r
- UINT32 ProcessorId;\r
- UINT32 Checksum;\r
- UINT32 LoaderRevision;\r
- UINT32 ProcessorFlags;\r
- UINT32 DataSize;\r
- UINT32 TotalSize;\r
- UINT8 Reserved[12];\r
-} EFI_CPU_MICROCODE_HEADER;\r
-\r
-typedef struct {\r
- UINT32 ExtendedSignatureCount;\r
- UINT32 ExtendedTableChecksum;\r
- UINT8 Reserved[12];\r
-} EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER;\r
-\r
-typedef struct {\r
- UINT32 ProcessorSignature;\r
- UINT32 ProcessorFlag;\r
- UINT32 ProcessorChecksum;\r
-} EFI_CPU_MICROCODE_EXTENDED_TABLE;\r
-\r
-//\r
-// The MS compiler doesn't handle QWORDs very well. So break\r
-// them into DWORDs to circumvent the problem.\r
-//\r
-typedef union _MSR_REGISTER {\r
- UINT64 Qword;\r
-\r
- struct _DWORDS {\r
- UINT32 Low;\r
- UINT32 High;\r
- } Dwords;\r
-\r
- struct _BYTES {\r
- UINT8 FirstByte;\r
- UINT8 SecondByte;\r
- UINT8 ThirdByte;\r
- UINT8 FouthByte;\r
- UINT8 FifthByte;\r
- UINT8 SixthByte;\r
- UINT8 SeventhByte;\r
- UINT8 EighthByte;\r
- } Bytes;\r
-\r
-} MSR_REGISTER;\r
-\r
-#pragma pack()\r
-\r
-//\r
-// Definition for CPUID Index\r
-//\r
-#define EFI_CPUID_SIGNATURE 0x0\r
-#define EFI_CPUID_VERSION_INFO 0x1\r
-#define EFI_CPUID_CACHE_INFO 0x2\r
-#define EFI_CPUID_SERIAL_NUMBER 0x3\r
-#define EFI_CPUID_EXTENDED_FUNCTION 0x80000000\r
-#define EFI_CPUID_EXTENDED_CPU_SIG 0x80000001\r
-#define EFI_CPUID_BRAND_STRING1 0x80000002\r
-#define EFI_CPUID_BRAND_STRING2 0x80000003\r
-#define EFI_CPUID_BRAND_STRING3 0x80000004\r
-#define EFI_CPUID_ADDRESS_SIZE 0x80000008\r
-\r
-//\r
-// Definition for MSR address\r
-//\r
-#define EFI_MSR_IA32_PLATFORM_ID 0x17\r
-#define EFI_MSR_IA32_APIC_BASE 0x1B\r
-#define EFI_MSR_EBC_HARD_POWERON 0x2A\r
-#define EFI_MSR_EBC_SOFT_POWERON 0x2B\r
-#define EFI_MSR_EBC_FREQUENCY_ID 0x2C\r
-#define MSR_IA32_FEATURE_CONTROL 0x3A\r
-#define EFI_MSR_IA32_BIOS_UPDT_TRIG 0x79\r
-#define EFI_MSR_IA32_BIOS_SIGN_ID 0x8B\r
-#define EFI_MSR_PSB_CLOCK_STATUS 0xCD\r
-#define MSR_EXT_CONFIG 0xEE\r
-#define EFI_IA32_MCG_CAP 0x179\r
-#define EFI_IA32_MCG_CTL 0x17B\r
-\r
-#define EFI_MSR_IA32_PERF_STS 0x198\r
-#define EFI_MSR_IA32_PERF_CTL 0x199\r
-#define EFI_MSR_IA32_CLOCK_MODULATION 0x19A\r
-#define MSR_IA32_THERMAL_INTERRUPT 0x19B\r
-#define EFI_MSR_IA32_THERM_STATUS 0x19C\r
-#define EFI_MSR_GV_THERM 0x19D\r
-#define MSR_IA32_MISC_ENABLE 0x1A0\r
-#define MSR_PIC_SENS_CFG 0x1AA\r
-\r
-#define EFI_IA32_MC0_CTL 0x400\r
-#define EFI_IA32_MC0_STATUS 0x401\r
-#define MSR_PECI_CONTROL 0x5A0\r
-\r
-//\r
-// Definition for MTRR address and related values\r
-//\r
-#define EFI_IA32_MTRR_FIX64K_00000 0x250\r
-#define EFI_IA32_MTRR_FIX16K_80000 0x258\r
-#define EFI_IA32_MTRR_FIX16K_A0000 0x259\r
-#define EFI_IA32_MTRR_FIX4K_C0000 0x268\r
-#define EFI_IA32_MTRR_FIX4K_C8000 0x269\r
-#define EFI_IA32_MTRR_FIX4K_D0000 0x26A\r
-#define EFI_IA32_MTRR_FIX4K_D8000 0x26B\r
-#define EFI_IA32_MTRR_FIX4K_E0000 0x26C\r
-#define EFI_IA32_MTRR_FIX4K_E8000 0x26D\r
-#define EFI_IA32_MTRR_FIX4K_F0000 0x26E\r
-#define EFI_IA32_MTRR_FIX4K_F8000 0x26F\r
-#define EFI_CACHE_VARIABLE_MTRR_BASE 0x200\r
-#define EFI_CACHE_VARIABLE_MTRR_END 0x20F\r
-#define EFI_CACHE_IA32_MTRR_DEF_TYPE 0x2FF\r
-\r
-#define EFI_CACHE_VALID_ADDRESS 0xFFFFFF000\r
-#define EFI_MSR_VALID_MASK 0xFFFFFFFFF\r
-#define EFI_CACHE_MTRR_VALID 0x800\r
-#define EFI_CACHE_FIXED_MTRR_VALID 0x400\r
-\r
-#define EFI_CACHE_UNCACHEABLE 0\r
-#define EFI_CACHE_WRITECOMBINING 1\r
-#define EFI_CACHE_WRITETHROUGH 4\r
-#define EFI_CACHE_WRITEPROTECTED 5\r
-#define EFI_CACHE_WRITEBACK 6\r
-\r
-//\r
-// Definition for Local APIC registers and related values\r
-//\r
-#define LOCAL_APIC_LVT_TIMER 0x320\r
-#define LOCAL_APIC_TIMER_INIT_COUNT 0x380\r
-#define LOCAL_APIC_TIMER_COUNT 0x390\r
-#define LOCAL_APIC_TIMER_DIVIDE 0x3E0\r
-\r
-\r
-#define DELIVERY_MODE_FIXED 0x0\r
-#define DELIVERY_MODE_LOWEST_PRIORITY 0x1\r
-#define DELIVERY_MODE_SMI 0x2\r
-#define DELIVERY_MODE_REMOTE_READ 0x3\r
-#define DELIVERY_MODE_NMI 0x4\r
-#define DELIVERY_MODE_INIT 0x5\r
-#define DELIVERY_MODE_SIPI 0x6\r
-\r
-#define TRIGGER_MODE_EDGE 0x0\r
-#define TRIGGER_MODE_LEVEL 0x1\r
-\r
-//\r
-// CPU System Memory Map Definition\r
-//\r
-#define CPU_MSI_MEMORY_BASE 0xFEE00000\r
-#define CPU_MSI_MEMORY_SIZE 0x100000\r
-\r
-\r
-#endif\r
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