+++ /dev/null
-/*++\r
-\r
-Copyright (c) 2005 - 2016, Intel Corporation. All rights reserved.<BR>\r
-(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>\r
-This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-\r
-Module Name:\r
-\r
- PciEnumeratorSupport.c\r
- \r
-Abstract:\r
-\r
- PCI Bus Driver\r
-\r
-Revision History\r
-\r
---*/\r
-\r
-#include "PciBus.h"\r
-\r
-EFI_STATUS \r
-InitializePPB (\r
- IN PCI_IO_DEVICE *PciIoDevice \r
-);\r
-\r
-EFI_STATUS \r
-InitializeP2C (\r
- IN PCI_IO_DEVICE *PciIoDevice \r
-);\r
-\r
-PCI_IO_DEVICE* \r
-CreatePciIoDevice (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
- IN PCI_TYPE00 *Pci,\r
- UINT8 Bus,\r
- UINT8 Device,\r
- UINT8 Func\r
-);\r
-\r
-\r
-PCI_IO_DEVICE*\r
-GatherP2CInfo (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
- IN PCI_TYPE00 *Pci,\r
- UINT8 Bus,\r
- UINT8 Device,\r
- UINT8 Func\r
-);\r
-\r
-UINTN\r
-PciParseBar (\r
- IN PCI_IO_DEVICE *PciIoDevice,\r
- IN UINTN Offset,\r
- IN UINTN BarIndex\r
-);\r
-\r
-\r
-EFI_STATUS\r
-PciSearchDevice (\r
- IN PCI_IO_DEVICE *Bridge,\r
- PCI_TYPE00 *Pci,\r
- UINT8 Bus,\r
- UINT8 Device,\r
- UINT8 Func,\r
- PCI_IO_DEVICE **PciDevice\r
-);\r
-\r
-\r
-EFI_STATUS \r
-DetermineDeviceAttribute (\r
- IN PCI_IO_DEVICE *PciIoDevice\r
-);\r
-\r
-EFI_STATUS \r
-BarExisted (\r
- IN PCI_IO_DEVICE *PciIoDevice,\r
- IN UINTN Offset,\r
- OUT UINT32 *BarLengthValue,\r
- OUT UINT32 *OriginalBarValue\r
- );\r
-\r
-\r
-\r
-EFI_DEVICE_PATH_PROTOCOL*\r
-CreatePciDevicePath(\r
- IN EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath,\r
- IN PCI_IO_DEVICE *PciIoDevice \r
-);\r
-\r
-PCI_IO_DEVICE* \r
-GatherDeviceInfo (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
- IN PCI_TYPE00 *Pci,\r
- UINT8 Bus,\r
- UINT8 Device,\r
- UINT8 Func\r
-);\r
-\r
-PCI_IO_DEVICE* \r
-GatherPPBInfo (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
- IN PCI_TYPE00 *Pci,\r
- UINT8 Bus,\r
- UINT8 Device,\r
- UINT8 Func\r
-);\r
-\r
-EFI_STATUS\r
-PciDevicePresent (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
- PCI_TYPE00 *Pci,\r
- UINT8 Bus,\r
- UINT8 Device,\r
- UINT8 Func\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- This routine is used to check whether the pci device is present\r
-\r
-Arguments:\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-{\r
- UINT64 Address;\r
- EFI_STATUS Status;\r
-\r
- //\r
- // Create PCI address map in terms of Bus, Device and Func\r
- //\r
- Address = EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r
-\r
- //\r
- // Read the Vendor Id register\r
- //\r
- Status = PciRootBridgeIo->Pci.Read (\r
- PciRootBridgeIo,\r
- EfiPciWidthUint32,\r
- Address,\r
- 1,\r
- Pci\r
- );\r
-\r
- if (!EFI_ERROR (Status) && (Pci->Hdr).VendorId != 0xffff) {\r
-\r
- //\r
- // Read the entire config header for the device\r
- //\r
-\r
- Status = PciRootBridgeIo->Pci.Read (\r
- PciRootBridgeIo,\r
- EfiPciWidthUint32,\r
- Address,\r
- sizeof (PCI_TYPE00) / sizeof (UINT32),\r
- Pci\r
- );\r
-\r
- return EFI_SUCCESS;\r
- }\r
-\r
- return EFI_NOT_FOUND;\r
-}\r
-\r
-EFI_STATUS\r
-PciPciDeviceInfoCollector (\r
- IN PCI_IO_DEVICE *Bridge,\r
- UINT8 StartBusNumber\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-{\r
- EFI_STATUS Status;\r
- PCI_TYPE00 Pci;\r
- UINT8 Device;\r
- UINT8 Func;\r
- UINT8 SecBus;\r
- PCI_IO_DEVICE *PciIoDevice;\r
- EFI_PCI_IO_PROTOCOL *PciIo;\r
-\r
- Status = EFI_SUCCESS;\r
- SecBus = 0;\r
- PciIoDevice = NULL;\r
-\r
- for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
-\r
- for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {\r
-\r
- //\r
- // Check to see whether PCI device is present\r
- //\r
-\r
- Status = PciDevicePresent (\r
- Bridge->PciRootBridgeIo,\r
- &Pci,\r
- (UINT8) StartBusNumber,\r
- (UINT8) Device,\r
- (UINT8) Func\r
- );\r
-\r
- if (EFI_ERROR (Status) && Func == 0) {\r
- //\r
- // go to next device if there is no Function 0\r
- //\r
- break;\r
- }\r
-\r
- if (!EFI_ERROR (Status)) {\r
-\r
- //\r
- // Collect all the information about the PCI device discovered\r
- //\r
- Status = PciSearchDevice (\r
- Bridge,\r
- &Pci,\r
- (UINT8) StartBusNumber,\r
- Device,\r
- Func,\r
- &PciIoDevice\r
- );\r
-\r
- //\r
- // Recursively scan PCI busses on the other side of PCI-PCI bridges\r
- //\r
- //\r
-\r
- if (!EFI_ERROR (Status) && (IS_PCI_BRIDGE (&Pci) || IS_CARDBUS_BRIDGE (&Pci))) {\r
-\r
- //\r
- // If it is PPB, we need to get the secondary bus to continue the enumeration\r
- //\r
- PciIo = &(PciIoDevice->PciIo);\r
-\r
- Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x19, 1, &SecBus);\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
- \r
- //\r
- // If the PCI bridge is initialized then enumerate the next level bus\r
- //\r
- if (SecBus != 0) {\r
- Status = PciPciDeviceInfoCollector (\r
- PciIoDevice,\r
- (UINT8) (SecBus)\r
- );\r
- }\r
- }\r
-\r
- if (Func == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {\r
-\r
- //\r
- // Skip sub functions, this is not a multi function device\r
- //\r
- Func = PCI_MAX_FUNC;\r
- }\r
- }\r
-\r
- }\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-EFI_STATUS\r
-PciSearchDevice (\r
- IN PCI_IO_DEVICE *Bridge,\r
- IN PCI_TYPE00 *Pci,\r
- IN UINT8 Bus,\r
- IN UINT8 Device,\r
- IN UINT8 Func,\r
- OUT PCI_IO_DEVICE **PciDevice\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Search required device.\r
-\r
-Arguments:\r
-\r
- Bridge - A pointer to the PCI_IO_DEVICE.\r
- Pci - A pointer to the PCI_TYPE00.\r
- Bus - Bus number.\r
- Device - Device number.\r
- Func - Function number.\r
- PciDevice - The Required pci device.\r
-\r
-Returns:\r
-\r
- Status code.\r
-\r
---*/\r
-{\r
- PCI_IO_DEVICE *PciIoDevice;\r
-\r
- PciIoDevice = NULL;\r
-\r
- if (!IS_PCI_BRIDGE (Pci)) {\r
-\r
- if (IS_CARDBUS_BRIDGE (Pci)) {\r
- PciIoDevice = GatherP2CInfo (\r
- Bridge->PciRootBridgeIo,\r
- Pci,\r
- Bus,\r
- Device,\r
- Func\r
- );\r
- if ((PciIoDevice != NULL) && (gFullEnumeration == TRUE)) {\r
- InitializeP2C (PciIoDevice);\r
- }\r
- } else {\r
-\r
- //\r
- // Create private data for Pci Device\r
- //\r
- PciIoDevice = GatherDeviceInfo (\r
- Bridge->PciRootBridgeIo,\r
- Pci,\r
- Bus,\r
- Device,\r
- Func\r
- );\r
-\r
- }\r
-\r
- } else {\r
-\r
- //\r
- // Create private data for PPB\r
- //\r
- PciIoDevice = GatherPPBInfo (\r
- Bridge->PciRootBridgeIo,\r
- Pci,\r
- Bus,\r
- Device,\r
- Func\r
- );\r
-\r
- //\r
- // Special initialization for PPB including making the PPB quiet\r
- //\r
- if ((PciIoDevice != NULL) && (gFullEnumeration == TRUE)) {\r
- InitializePPB (PciIoDevice);\r
- }\r
- }\r
-\r
- if (!PciIoDevice) {\r
- return EFI_OUT_OF_RESOURCES;\r
- }\r
- \r
- //\r
- // Create a device path for this PCI device and store it into its private data\r
- //\r
- CreatePciDevicePath(\r
- Bridge->DevicePath,\r
- PciIoDevice \r
- );\r
- \r
- //\r
- // Detect this function has option rom\r
- //\r
- if (gFullEnumeration) {\r
-\r
- if (!IS_CARDBUS_BRIDGE (Pci)) {\r
-\r
- GetOpRomInfo (PciIoDevice);\r
-\r
- }\r
-\r
- ResetPowerManagementFeature (PciIoDevice);\r
- \r
- } \r
- else {\r
- PciRomGetRomResourceFromPciOptionRomTable (\r
- &gPciBusDriverBinding,\r
- PciIoDevice->PciRootBridgeIo,\r
- PciIoDevice\r
- );\r
- }\r
-\r
- \r
- //\r
- // Insert it into a global tree for future reference\r
- //\r
- InsertPciDevice (Bridge, PciIoDevice);\r
-\r
- //\r
- // Determine PCI device attributes\r
- //\r
- DetermineDeviceAttribute (PciIoDevice);\r
-\r
- if (PciDevice != NULL) {\r
- *PciDevice = PciIoDevice;\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-PCI_IO_DEVICE *\r
-GatherDeviceInfo (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
- IN PCI_TYPE00 *Pci,\r
- UINT8 Bus,\r
- UINT8 Device,\r
- UINT8 Func\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-{\r
- UINTN Offset;\r
- UINTN BarIndex;\r
- PCI_IO_DEVICE *PciIoDevice;\r
-\r
- PciIoDevice = CreatePciIoDevice (\r
- PciRootBridgeIo,\r
- Pci,\r
- Bus,\r
- Device,\r
- Func\r
- );\r
-\r
- if (!PciIoDevice) {\r
- return NULL;\r
- }\r
-\r
- //\r
- // If it is a full enumeration, disconnect the device in advance\r
- //\r
- if (gFullEnumeration) {\r
-\r
- PciDisableCommandRegister (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);\r
-\r
- }\r
-\r
- //\r
- // Start to parse the bars\r
- //\r
- for (Offset = 0x10, BarIndex = 0; Offset <= 0x24; BarIndex++) {\r
- Offset = PciParseBar (PciIoDevice, Offset, BarIndex);\r
- }\r
-\r
- return PciIoDevice;\r
-}\r
-\r
-PCI_IO_DEVICE *\r
-GatherPPBInfo (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
- IN PCI_TYPE00 *Pci,\r
- UINT8 Bus,\r
- UINT8 Device,\r
- UINT8 Func\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-{\r
- PCI_IO_DEVICE *PciIoDevice;\r
- EFI_STATUS Status;\r
- UINT8 Value;\r
- EFI_PCI_IO_PROTOCOL *PciIo;\r
- UINT8 Temp;\r
-\r
- PciIoDevice = CreatePciIoDevice (\r
- PciRootBridgeIo,\r
- Pci,\r
- Bus,\r
- Device,\r
- Func\r
- );\r
-\r
- if (!PciIoDevice) {\r
- return NULL;\r
- }\r
- \r
- if (gFullEnumeration) {\r
- PciDisableCommandRegister (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);\r
-\r
- //\r
- // Initalize the bridge control register\r
- //\r
- PciDisableBridgeControlRegister (PciIoDevice, EFI_PCI_BRIDGE_CONTROL_BITS_OWNED);\r
- }\r
-\r
- PciIo = &PciIoDevice->PciIo;\r
-\r
- //\r
- // Test whether it support 32 decode or not\r
- //\r
- PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);\r
- PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Value);\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);\r
-\r
- if (Value) {\r
- if (Value & 0x01) {\r
- PciIoDevice->Decodes |= EFI_BRIDGE_IO32_DECODE_SUPPORTED;\r
- } else {\r
- PciIoDevice->Decodes |= EFI_BRIDGE_IO16_DECODE_SUPPORTED;\r
- }\r
- }\r
-\r
- Status = BarExisted (\r
- PciIoDevice,\r
- 0x24,\r
- NULL,\r
- NULL\r
- );\r
-\r
- //\r
- // test if it supports 64 memory or not\r
- //\r
- if (!EFI_ERROR (Status)) {\r
-\r
- Status = BarExisted (\r
- PciIoDevice,\r
- 0x28,\r
- NULL,\r
- NULL\r
- );\r
-\r
- if (!EFI_ERROR (Status)) {\r
- PciIoDevice->Decodes |= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED;\r
- PciIoDevice->Decodes |= EFI_BRIDGE_PMEM64_DECODE_SUPPORTED;\r
- } else {\r
- PciIoDevice->Decodes |= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED;\r
- }\r
- }\r
-\r
- //\r
- // Memory 32 code is required for ppb\r
- //\r
- PciIoDevice->Decodes |= EFI_BRIDGE_MEM32_DECODE_SUPPORTED;\r
-\r
- return PciIoDevice;\r
-}\r
-\r
-PCI_IO_DEVICE *\r
-GatherP2CInfo (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
- IN PCI_TYPE00 *Pci,\r
- UINT8 Bus,\r
- UINT8 Device,\r
- UINT8 Func\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-{\r
- PCI_IO_DEVICE *PciIoDevice;\r
- \r
- PciIoDevice = CreatePciIoDevice (\r
- PciRootBridgeIo,\r
- Pci,\r
- Bus,\r
- Device,\r
- Func\r
- );\r
-\r
- if (!PciIoDevice) {\r
- return NULL;\r
- }\r
-\r
- if (gFullEnumeration) {\r
- PciDisableCommandRegister (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);\r
-\r
- //\r
- // Initalize the bridge control register\r
- //\r
- PciDisableBridgeControlRegister (PciIoDevice, EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED);\r
-\r
- }\r
- //\r
- // P2C only has one bar that is in 0x10\r
- //\r
- PciParseBar(PciIoDevice, 0x10, 0);\r
- \r
- PciIoDevice->Decodes = EFI_BRIDGE_MEM32_DECODE_SUPPORTED |\r
- EFI_BRIDGE_PMEM32_DECODE_SUPPORTED |\r
- EFI_BRIDGE_IO32_DECODE_SUPPORTED;\r
-\r
- return PciIoDevice;\r
-}\r
-\r
-EFI_DEVICE_PATH_PROTOCOL *\r
-CreatePciDevicePath (\r
- IN EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath,\r
- IN PCI_IO_DEVICE *PciIoDevice\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-{\r
-\r
- PCI_DEVICE_PATH PciNode;\r
-\r
- //\r
- // Create PCI device path\r
- //\r
- PciNode.Header.Type = HARDWARE_DEVICE_PATH;\r
- PciNode.Header.SubType = HW_PCI_DP;\r
- SetDevicePathNodeLength (&PciNode.Header, sizeof (PciNode));\r
-\r
- PciNode.Device = PciIoDevice->DeviceNumber;\r
- PciNode.Function = PciIoDevice->FunctionNumber;\r
- PciIoDevice->DevicePath = AppendDevicePathNode (ParentDevicePath, &PciNode.Header);\r
-\r
- return PciIoDevice->DevicePath;\r
-}\r
-\r
-EFI_STATUS\r
-BarExisted (\r
- IN PCI_IO_DEVICE *PciIoDevice,\r
- IN UINTN Offset,\r
- OUT UINT32 *BarLengthValue,\r
- OUT UINT32 *OriginalBarValue\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Check the bar is existed or not.\r
-\r
-Arguments:\r
-\r
- PciIoDevice - A pointer to the PCI_IO_DEVICE.\r
- Offset - The offset.\r
- BarLengthValue - The bar length value.\r
- OriginalBarValue - The original bar value.\r
-\r
-Returns:\r
-\r
- EFI_NOT_FOUND - The bar don't exist.\r
- EFI_SUCCESS - The bar exist.\r
-\r
---*/\r
-{\r
- EFI_PCI_IO_PROTOCOL *PciIo;\r
- UINT32 OriginalValue;\r
- UINT32 Value;\r
- EFI_TPL OldTpl;\r
-\r
- PciIo = &PciIoDevice->PciIo;\r
-\r
- //\r
- // Preserve the original value\r
- //\r
-\r
- PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);\r
-\r
- //\r
- // Raise TPL to high level to disable timer interrupt while the BAR is probed\r
- //\r
- OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);\r
-\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &gAllOne);\r
- PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &Value);\r
-\r
- //\r
- // Write back the original value\r
- //\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);\r
-\r
- //\r
- // Restore TPL to its original level\r
- //\r
- gBS->RestoreTPL (OldTpl);\r
-\r
- if (BarLengthValue != NULL) {\r
- *BarLengthValue = Value;\r
- }\r
-\r
- if (OriginalBarValue != NULL) {\r
- *OriginalBarValue = OriginalValue;\r
- }\r
-\r
- if (Value == 0) {\r
- return EFI_NOT_FOUND;\r
- } else {\r
- return EFI_SUCCESS;\r
- }\r
-}\r
-\r
-\r
-EFI_STATUS\r
-DetermineDeviceAttribute (\r
- IN PCI_IO_DEVICE *PciIoDevice\r
- )\r
-/*++\r
-\r
-Routine Description:\r
- \r
- Determine the related attributes of all devices under a Root Bridge\r
-\r
-Arguments:\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-{\r
- UINT16 Command;\r
- UINT16 BridgeControl;\r
-\r
- Command = 0;\r
-\r
- PciIoDevice->Supports |= EFI_PCI_DEVICE_ENABLE;\r
- PciIoDevice->Supports |= EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE;\r
-\r
- if (IS_PCI_VGA (&(PciIoDevice->Pci))){\r
-\r
- //\r
- // If the device is VGA, VGA related Attributes are supported\r
- //\r
- PciIoDevice->Supports |= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO ;\r
- PciIoDevice->Supports |= EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY ;\r
- PciIoDevice->Supports |= EFI_PCI_IO_ATTRIBUTE_VGA_IO ;\r
- }\r
-\r
- if(IS_ISA_BRIDGE(&(PciIoDevice->Pci)) || IS_INTEL_ISA_BRIDGE(&(PciIoDevice->Pci))) {\r
- //\r
- // If the devie is a ISA Bridge, set the two attributes\r
- //\r
- PciIoDevice->Supports |= EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO;\r
- PciIoDevice->Supports |= EFI_PCI_IO_ATTRIBUTE_ISA_IO;\r
- }\r
-\r
- if (IS_PCI_GFX (&(PciIoDevice->Pci))) {\r
-\r
- //\r
- // If the device is GFX, then only set the EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO\r
- // attribute\r
- //\r
- PciIoDevice->Supports |= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO ;\r
- }\r
-\r
-\r
- //\r
- // If the device is IDE, IDE related attributes are supported\r
- //\r
- if (IS_PCI_IDE (&(PciIoDevice->Pci))) {\r
- PciIoDevice->Supports |= EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO ;\r
- PciIoDevice->Supports |= EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO ;\r
- }\r
-\r
- PciReadCommandRegister(PciIoDevice, &Command);\r
-\r
- \r
- if (Command & EFI_PCI_COMMAND_IO_SPACE) {\r
- PciIoDevice->Attributes |= EFI_PCI_IO_ATTRIBUTE_IO;\r
- }\r
-\r
- if (Command & EFI_PCI_COMMAND_MEMORY_SPACE) {\r
- PciIoDevice->Attributes |= EFI_PCI_IO_ATTRIBUTE_MEMORY;\r
- }\r
-\r
- if (Command & EFI_PCI_COMMAND_BUS_MASTER) {\r
- PciIoDevice->Attributes |= EFI_PCI_IO_ATTRIBUTE_BUS_MASTER;\r
- }\r
-\r
- if (IS_PCI_BRIDGE (&(PciIoDevice->Pci)) || \r
- IS_CARDBUS_BRIDGE (&(PciIoDevice->Pci))){\r
-\r
- //\r
- // If it is a PPB, read the Bridge Control Register to determine\r
- // the relevant attributes\r
- //\r
- BridgeControl = 0;\r
- PciReadBridgeControlRegister(PciIoDevice, &BridgeControl);\r
-\r
- //\r
- // Determine whether the ISA bit is set\r
- // If ISA Enable on Bridge is set, the PPB\r
- // will block forwarding 0x100-0x3ff for each 1KB in the \r
- // first 64KB I/O range.\r
- //\r
- if ((BridgeControl & EFI_PCI_BRIDGE_CONTROL_ISA) != 0) {\r
- PciIoDevice->Attributes |= EFI_PCI_IO_ATTRIBUTE_ISA_IO;\r
- } \r
-\r
- //\r
- // Determine whether the VGA bit is set\r
- // If it is set, the bridge is set to decode VGA memory range\r
- // and palette register range\r
- //\r
- if (IS_PCI_VGA (&(PciIoDevice->Pci)) &&BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA) {\r
- PciIoDevice->Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_IO;\r
- PciIoDevice->Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY;\r
- PciIoDevice->Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO;\r
- }\r
-\r
- //\r
- // if the palette snoop bit is set, then the brige is set to \r
- // decode palette IO write\r
- //\r
- if (Command & EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) {\r
- PciIoDevice->Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO;\r
- }\r
- } \r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-UINTN\r
-PciParseBar (\r
- IN PCI_IO_DEVICE *PciIoDevice,\r
- IN UINTN Offset,\r
- IN UINTN BarIndex\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-{\r
- UINT32 Value;\r
- UINT32 OriginalValue;\r
- UINT32 Mask;\r
- EFI_STATUS Status;\r
-\r
- OriginalValue = 0;\r
- Value = 0;\r
-\r
- Status = BarExisted (\r
- PciIoDevice,\r
- Offset,\r
- &Value,\r
- &OriginalValue\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- PciIoDevice->PciBar[BarIndex].BaseAddress = 0;\r
- PciIoDevice->PciBar[BarIndex].Length = 0;\r
- PciIoDevice->PciBar[BarIndex].Alignment = 0;\r
-\r
- //\r
- // Some devices don't fully comply to PCI spec 2.2. So be to scan all the BARs anyway\r
- //\r
- PciIoDevice->PciBar[BarIndex].Offset = (UINT8) Offset;\r
- return Offset + 4;\r
- }\r
-\r
- PciIoDevice->PciBar[BarIndex].Offset = (UINT8) Offset;\r
- if (Value & 0x01) {\r
- //\r
- // Device I/Os\r
- //\r
- Mask = 0xfffffffc;\r
-\r
- if (Value & 0xFFFF0000) {\r
- //\r
- // It is a IO32 bar\r
- //\r
- PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeIo32;\r
- PciIoDevice->PciBar[BarIndex].Length = ((~(Value & Mask)) + 1);\r
- PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;\r
-\r
- } else {\r
- //\r
- // It is a IO16 bar\r
- //\r
- PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeIo16;\r
- PciIoDevice->PciBar[BarIndex].Length = 0x0000FFFF & ((~(Value & Mask)) + 1);\r
- PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;\r
-\r
- }\r
- //\r
- // Workaround. Some platforms inplement IO bar with 0 length\r
- // Need to treat it as no-bar\r
- //\r
- if (PciIoDevice->PciBar[BarIndex].Length == 0) {\r
- PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeUnknown;\r
- }\r
-\r
- PciIoDevice->PciBar[BarIndex].Prefetchable = FALSE;\r
- PciIoDevice->PciBar[BarIndex].BaseAddress = OriginalValue & Mask;\r
-\r
- } else {\r
-\r
- Mask = 0xfffffff0;\r
-\r
- PciIoDevice->PciBar[BarIndex].BaseAddress = OriginalValue & Mask;\r
-\r
- switch (Value & 0x07) {\r
-\r
- //\r
- //memory space; anywhere in 32 bit address space\r
- //\r
- case 0x00:\r
- if (Value & 0x08) {\r
- PciIoDevice->PciBar[BarIndex].BarType = PciBarTypePMem32;\r
- } else {\r
- PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeMem32;\r
- }\r
-\r
- PciIoDevice->PciBar[BarIndex].Length = (~(Value & Mask)) + 1;\r
- PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;\r
-\r
- break;\r
-\r
- //\r
- // memory space; anywhere in 64 bit address space\r
- //\r
- case 0x04:\r
- if (Value & 0x08) {\r
- PciIoDevice->PciBar[BarIndex].BarType = PciBarTypePMem64;\r
- } else {\r
- PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeMem64;\r
- }\r
-\r
- //\r
- // According to PCI 2.2,if the bar indicates a memory 64 decoding, next bar\r
- // is regarded as an extension for the first bar. As a result\r
- // the sizing will be conducted on combined 64 bit value\r
- // Here just store the masked first 32bit value for future size\r
- // calculation\r
- //\r
- PciIoDevice->PciBar[BarIndex].Length = Value & Mask;\r
- PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;\r
-\r
- //\r
- // Increment the offset to point to next DWORD\r
- //\r
- Offset += 4;\r
-\r
- Status = BarExisted (\r
- PciIoDevice,\r
- Offset,\r
- &Value,\r
- &OriginalValue\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Offset + 4;\r
- }\r
-\r
- //\r
- // Fix the length to support some spefic 64 bit BAR\r
- //\r
- Value |= ((UINT32)(-1) << HighBitSet32 (Value)); \r
-\r
- //\r
- // Calculate the size of 64bit bar\r
- //\r
- PciIoDevice->PciBar[BarIndex].BaseAddress |= LShiftU64 ((UINT64) OriginalValue, 32);\r
-\r
- PciIoDevice->PciBar[BarIndex].Length = PciIoDevice->PciBar[BarIndex].Length | LShiftU64 ((UINT64) Value, 32);\r
- PciIoDevice->PciBar[BarIndex].Length = (~(PciIoDevice->PciBar[BarIndex].Length)) + 1;\r
- PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;\r
-\r
- break;\r
-\r
- //\r
- // reserved\r
- //\r
- default:\r
- PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeUnknown;\r
- PciIoDevice->PciBar[BarIndex].Length = (~(Value & Mask)) + 1;\r
- PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;\r
-\r
- break;\r
- }\r
- }\r
- \r
- //\r
- // Check the length again so as to keep compatible with some special bars\r
- //\r
- if (PciIoDevice->PciBar[BarIndex].Length == 0) {\r
- PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeUnknown;\r
- PciIoDevice->PciBar[BarIndex].BaseAddress = 0;\r
- PciIoDevice->PciBar[BarIndex].Alignment = 0;\r
- }\r
- \r
- //\r
- // Increment number of bar\r
- //\r
- return Offset + 4;\r
-}\r
-\r
-EFI_STATUS\r
-InitializePPB (\r
- IN PCI_IO_DEVICE *PciIoDevice\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-{\r
- EFI_PCI_IO_PROTOCOL *PciIo;\r
-\r
- PciIo = &(PciIoDevice->PciIo);\r
-\r
- //\r
- // Put all the resource apertures including IO16\r
- // Io32, pMem32, pMem64 to quiescent state\r
- // Resource base all ones, Resource limit all zeros\r
- //\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1D, 1, &gAllZero);\r
-\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x20, 1, &gAllOne);\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x22, 1, &gAllZero);\r
-\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x24, 1, &gAllOne);\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x26, 1, &gAllZero);\r
-\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllOne);\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x2C, 1, &gAllZero);\r
-\r
- //\r
- // don't support use io32 as for now\r
- //\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x30, 1, &gAllOne);\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x32, 1, &gAllZero);\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-EFI_STATUS\r
-InitializeP2C (\r
- IN PCI_IO_DEVICE *PciIoDevice\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-{\r
- EFI_PCI_IO_PROTOCOL *PciIo;\r
-\r
- PciIo = &(PciIoDevice->PciIo);\r
-\r
- //\r
- // Put all the resource apertures including IO16\r
- // Io32, pMem32, pMem64 to quiescent state(\r
- // Resource base all ones, Resource limit all zeros\r
- //\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x1c, 1, &gAllOne);\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x20, 1, &gAllZero);\r
-\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x24, 1, &gAllOne);\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllZero);\r
-\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x2c, 1, &gAllOne);\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x30, 1, &gAllZero);\r
-\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x34, 1, &gAllOne);\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x38, 1, &gAllZero);\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-PCI_IO_DEVICE *\r
-CreatePciIoDevice (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
- IN PCI_TYPE00 *Pci,\r
- UINT8 Bus,\r
- UINT8 Device,\r
- UINT8 Func\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-{\r
-\r
- EFI_STATUS Status;\r
- PCI_IO_DEVICE *PciIoDevice;\r
-\r
- PciIoDevice = NULL;\r
-\r
- Status = gBS->AllocatePool (\r
- EfiBootServicesData,\r
- sizeof (PCI_IO_DEVICE),\r
- (VOID **) &PciIoDevice\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- return NULL;\r
- }\r
-\r
- ZeroMem (PciIoDevice, sizeof (PCI_IO_DEVICE));\r
-\r
- PciIoDevice->Signature = PCI_IO_DEVICE_SIGNATURE;\r
- PciIoDevice->Handle = NULL;\r
- PciIoDevice->PciRootBridgeIo = PciRootBridgeIo;\r
- PciIoDevice->DevicePath = NULL;\r
- PciIoDevice->BusNumber = Bus;\r
- PciIoDevice->DeviceNumber = Device;\r
- PciIoDevice->FunctionNumber = Func;\r
- PciIoDevice->Decodes = 0;\r
- if (gFullEnumeration) {\r
- PciIoDevice->Allocated = FALSE;\r
- } else {\r
- PciIoDevice->Allocated = TRUE;\r
- }\r
-\r
- PciIoDevice->Attributes = 0;\r
- PciIoDevice->Supports = 0;\r
- PciIoDevice->BusOverride = FALSE;\r
- PciIoDevice->IsPciExp = FALSE;\r
-\r
- CopyMem (&(PciIoDevice->Pci), Pci, sizeof (PCI_TYPE01));\r
-\r
- //\r
- // Initialize the PCI I/O instance structure\r
- //\r
-\r
- Status = InitializePciIoInstance (PciIoDevice);\r
- Status = InitializePciDriverOverrideInstance (PciIoDevice);\r
-\r
- if (EFI_ERROR (Status)) {\r
- gBS->FreePool (PciIoDevice);\r
- return NULL;\r
- }\r
-\r
- //\r
- // Initialize the reserved resource list\r
- //\r
- InitializeListHead (&PciIoDevice->ReservedResourceList);\r
-\r
- //\r
- // Initialize the driver list\r
- //\r
- InitializeListHead (&PciIoDevice->OptionRomDriverList);\r
-\r
- //\r
- // Initialize the child list\r
- //\r
- InitializeListHead (&PciIoDevice->ChildList);\r
-\r
- return PciIoDevice;\r
-}\r
-\r
-EFI_STATUS\r
-PciEnumeratorLight (\r
- IN EFI_HANDLE Controller\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- This routine is used to enumerate entire pci bus system \r
- in a given platform\r
-\r
-Arguments:\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-{\r
-\r
- EFI_STATUS Status;\r
- EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
- PCI_IO_DEVICE *RootBridgeDev;\r
- UINT16 MinBus;\r
- UINT16 MaxBus;\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
-\r
- MinBus = 0;\r
- MaxBus = PCI_MAX_BUS;\r
- Descriptors = NULL;\r
-\r
- //\r
- // If this host bridge has been already enumerated, then return successfully\r
- //\r
- if (RootBridgeExisted (Controller)) {\r
- return EFI_SUCCESS;\r
- }\r
-\r
- //\r
- // Open the IO Abstraction(s) needed to perform the supported test\r
- //\r
- Status = gBS->OpenProtocol (\r
- Controller , \r
- &gEfiDevicePathProtocolGuid, \r
- (VOID **)&ParentDevicePath,\r
- gPciBusDriverBinding.DriverBindingHandle, \r
- Controller, \r
- EFI_OPEN_PROTOCOL_BY_DRIVER\r
- );\r
- if (EFI_ERROR (Status) && Status != EFI_ALREADY_STARTED) {\r
- return Status;\r
- }\r
-\r
- //\r
- // Open pci root bridge io protocol\r
- //\r
- Status = gBS->OpenProtocol (\r
- Controller,\r
- &gEfiPciRootBridgeIoProtocolGuid,\r
- (VOID **) &PciRootBridgeIo,\r
- gPciBusDriverBinding.DriverBindingHandle,\r
- Controller,\r
- EFI_OPEN_PROTOCOL_BY_DRIVER\r
- );\r
- if (EFI_ERROR (Status) && Status != EFI_ALREADY_STARTED) {\r
- return Status;\r
- }\r
-\r
- //\r
- // Load all EFI Drivers from all PCI Option ROMs behind the PCI Root Bridge \r
- //\r
- Status = PciRomLoadEfiDriversFromOptionRomTable (&gPciBusDriverBinding, PciRootBridgeIo);\r
-\r
- Status = PciRootBridgeIo->Configuration (PciRootBridgeIo, (VOID **) &Descriptors);\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- while (PciGetBusRange (&Descriptors, &MinBus, &MaxBus, NULL) == EFI_SUCCESS) {\r
-\r
- //\r
- // Create a device node for root bridge device with a NULL host bridge controller handle\r
- //\r
- RootBridgeDev = CreateRootBridge (Controller);\r
-\r
- //\r
- // Record the root bridge device path\r
- //\r
- RootBridgeDev->DevicePath = ParentDevicePath;\r
-\r
- //\r
- // Record the root bridge io protocol\r
- //\r
- RootBridgeDev->PciRootBridgeIo = PciRootBridgeIo;\r
-\r
- Status = PciPciDeviceInfoCollector (\r
- RootBridgeDev,\r
- (UINT8) MinBus\r
- );\r
-\r
- if (!EFI_ERROR (Status)) {\r
-\r
- //\r
- // If successfully, insert the node into device pool\r
- //\r
- InsertRootBridge (RootBridgeDev);\r
- } else {\r
-\r
- //\r
- // If unsuccessly, destroy the entire node\r
- //\r
- DestroyRootBridge (RootBridgeDev);\r
- }\r
-\r
- Descriptors++;\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-EFI_STATUS\r
-PciGetBusRange (\r
- IN EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,\r
- OUT UINT16 *MinBus,\r
- OUT UINT16 *MaxBus,\r
- OUT UINT16 *BusRange\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Get the bus range.\r
-\r
-Arguments:\r
-\r
- Descriptors - A pointer to the address space descriptor.\r
- MinBus - The min bus.\r
- MaxBus - The max bus.\r
- BusRange - The bus range.\r
- \r
-Returns:\r
- \r
- Status Code.\r
-\r
---*/\r
-{\r
-\r
- while ((*Descriptors)->Desc != ACPI_END_TAG_DESCRIPTOR) {\r
- if ((*Descriptors)->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {\r
- if (MinBus != NULL) {\r
- *MinBus = (UINT16)(*Descriptors)->AddrRangeMin;\r
- }\r
-\r
- if (MaxBus != NULL) {\r
- *MaxBus = (UINT16)(*Descriptors)->AddrRangeMax;\r
- }\r
-\r
- if (BusRange != NULL) {\r
- *BusRange = (UINT16)(*Descriptors)->AddrLen;\r
- }\r
- return EFI_SUCCESS;\r
- }\r
-\r
- (*Descriptors)++;\r
- }\r
-\r
- return EFI_NOT_FOUND;\r
-}\r
-\r
projects / mirror_edk2.git / blobdiff