/** @file\r
\r
- Copyright (c) 2017 - 2018, ARM Limited. All rights reserved.\r
+ Copyright (c) 2017 - 2019, ARM Limited. All rights reserved.\r
\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
@par Glossary:\r
- Cm or CM - Configuration Manager\r
EArmObjSmmuV3, ///< 22 - SMMUv3\r
EArmObjPmcg, ///< 23 - PMCG\r
EArmObjGicItsIdentifierArray, ///< 24 - GIC ITS Identifier Array\r
- EArmObjIdMapping, ///< 25 - ID Mapping\r
+ EArmObjIdMappingArray, ///< 25 - ID Mapping Array\r
EArmObjSmmuInterruptArray, ///< 26 - SMMU Interrupt Array\r
+ EArmObjProcHierarchyInfo, ///< 27 - Processor Hierarchy Info\r
+ EArmObjCacheInfo, ///< 28 - Cache Info\r
+ EArmObjProcNodeIdInfo, ///< 29 - Processor Hierarchy Node ID Info\r
+ EArmObjCmRef, ///< 30 - CM Object Reference\r
EArmObjMax\r
} EARM_OBJECT_ID;\r
\r
/** A structure that describes the\r
ARM Boot Architecture flags.\r
+\r
+ ID: EArmObjBootArchInfo\r
*/\r
typedef struct CmArmBootArchInfo {\r
/** This is the ARM_BOOT_ARCH flags field of the FADT Table\r
// Reserved for use when SMBIOS tables are implemented\r
} CM_ARM_CPU_INFO;\r
\r
-typedef struct CmArmCpuInfoList {\r
- UINT32 CpuCount;\r
- CM_ARM_CPU_INFO * CpuInfo;\r
-} CM_ARM_CPU_INFO_LIST;\r
-\r
/** A structure that describes the\r
Power Management Profile Information for the Platform.\r
+\r
+ ID: EArmObjPowerManagementProfileInfo\r
*/\r
typedef struct CmArmPowerManagementProfileInfo {\r
/** This is the Preferred_PM_Profile field of the FADT Table\r
\r
/** A structure that describes the\r
GIC CPU Interface for the Platform.\r
+\r
+ ID: EArmObjGicCInfo\r
*/\r
typedef struct CmArmGicCInfo {\r
/// The GIC CPU Interface number.\r
ACPI Specification.\r
*/\r
UINT8 ProcessorPowerEfficiencyClass;\r
+\r
+ /** Statistical Profiling Extension buffer overflow GSIV. Zero if\r
+ unsupported by this processor. This field was introduced in\r
+ ACPI 6.3 (MADT revision 5) and is therefore ignored when\r
+ generating MADT revision 4 or lower.\r
+ */\r
+ UINT16 SpeOverflowInterrupt;\r
} CM_ARM_GICC_INFO;\r
\r
/** A structure that describes the\r
GIC Distributor information for the Platform.\r
+\r
+ ID: EArmObjGicDInfo\r
*/\r
typedef struct CmArmGicDInfo {\r
- /// The GIC Distributor ID.\r
- UINT32 GicId;\r
-\r
/// The Physical Base address for the GIC Distributor.\r
UINT64 PhysicalBaseAddress;\r
\r
\r
/** A structure that describes the\r
GIC MSI Frame information for the Platform.\r
+\r
+ ID: EArmObjGicMsiFrameInfo\r
*/\r
typedef struct CmArmGicMsiFrameInfo {\r
/// The GIC MSI Frame ID\r
\r
/** A structure that describes the\r
GIC Redistributor information for the Platform.\r
+\r
+ ID: EArmObjGicRedistributorInfo\r
*/\r
typedef struct CmArmGicRedistInfo {\r
/** The physical address of a page range\r
\r
/** A structure that describes the\r
GIC Interrupt Translation Service information for the Platform.\r
+\r
+ ID: EArmObjGicItsInfo\r
*/\r
typedef struct CmArmGicItsInfo {\r
/// The GIC ITS ID\r
\r
/** A structure that describes the\r
Serial Port information for the Platform.\r
+\r
+ ID: EArmObjSerialConsolePortInfo or\r
+ EArmObjSerialDebugPortInfo\r
*/\r
typedef struct CmArmSerialPortInfo {\r
/// The physical base address for the serial port\r
\r
/** A structure that describes the\r
Generic Timer information for the Platform.\r
+\r
+ ID: EArmObjGenericTimerInfo\r
*/\r
typedef struct CmArmGenericTimerInfo {\r
/// The physical base address for the counter control frame\r
\r
/** A structure that describes the\r
Platform Generic Block Timer Frame information for the Platform.\r
+\r
+ ID: EArmObjGTBlockTimerFrameInfo\r
*/\r
typedef struct CmArmGTBlockTimerFrameInfo {\r
/// The Generic Timer frame number\r
\r
/** A structure that describes the\r
Platform Generic Block Timer information for the Platform.\r
+\r
+ ID: EArmObjPlatformGTBlockInfo\r
*/\r
typedef struct CmArmGTBlockInfo {\r
/// The physical base address for the GT Block Timer structure\r
\r
/** A structure that describes the\r
SBSA Generic Watchdog information for the Platform.\r
+\r
+ ID: EArmObjPlatformGenericWatchdogInfo\r
*/\r
typedef struct CmArmGenericWatchdogInfo {\r
/// The physical base address of the SBSA Watchdog control frame\r
\r
/** A structure that describes the\r
PCI Configuration Space information for the Platform.\r
+\r
+ ID: EArmObjPciConfigSpaceInfo\r
*/\r
typedef struct CmArmPciConfigSpaceInfo {\r
/// The physical base address for the PCI segment\r
\r
/** A structure that describes the\r
Hypervisor Vendor ID information for the Platform.\r
+\r
+ ID: EArmObjHypervisorVendorIdentity\r
*/\r
typedef struct CmArmHypervisorVendorId {\r
/// The hypervisor Vendor ID\r
\r
/** A structure that describes the\r
Fixed feature flags for the Platform.\r
+\r
+ ID: EArmObjFixedFeatureFlags\r
*/\r
typedef struct CmArmFixedFeatureFlags {\r
/// The Fixed feature flags\r
\r
/** A structure that describes the\r
ITS Group node for the Platform.\r
+\r
+ ID: EArmObjItsGroup\r
*/\r
typedef struct CmArmItsGroupNode {\r
- /// An unique token used to ideintify this object\r
+ /// An unique token used to identify this object\r
CM_OBJECT_TOKEN Token;\r
/// The number of ITS identifiers in the ITS node\r
UINT32 ItsIdCount;\r
\r
/** A structure that describes the\r
GIC ITS Identifiers for an ITS Group node.\r
+\r
+ ID: EArmObjGicItsIdentifierArray\r
*/\r
typedef struct CmArmGicItsIdentifier {\r
/// The ITS Identifier\r
\r
/** A structure that describes the\r
Named component node for the Platform.\r
+\r
+ ID: EArmObjNamedComponent\r
*/\r
typedef struct CmArmNamedComponentNode {\r
- /// An unique token used to ideintify this object\r
+ /// An unique token used to identify this object\r
CM_OBJECT_TOKEN Token;\r
/// Number of ID mappings\r
UINT32 IdMappingCount;\r
\r
/** A structure that describes the\r
Root complex node for the Platform.\r
+\r
+ ID: EArmObjRootComplex\r
*/\r
typedef struct CmArmRootComplexNode {\r
- /// An unique token used to ideintify this object\r
+ /// An unique token used to identify this object\r
CM_OBJECT_TOKEN Token;\r
/// Number of ID mappings\r
UINT32 IdMappingCount;\r
\r
/** A structure that describes the\r
SMMUv1 or SMMUv2 node for the Platform.\r
+\r
+ ID: EArmObjSmmuV1SmmuV2\r
*/\r
typedef struct CmArmSmmuV1SmmuV2Node {\r
- /// An unique token used to ideintify this object\r
+ /// An unique token used to identify this object\r
CM_OBJECT_TOKEN Token;\r
/// Number of ID mappings\r
UINT32 IdMappingCount;\r
\r
/** A structure that describes the\r
SMMUv3 node for the Platform.\r
+\r
+ ID: EArmObjSmmuV3\r
*/\r
typedef struct CmArmSmmuV3Node {\r
- /// An unique token used to ideintify this object\r
+ /// An unique token used to identify this object\r
CM_OBJECT_TOKEN Token;\r
/// Number of ID mappings\r
UINT32 IdMappingCount;\r
\r
/** A structure that describes the\r
PMCG node for the Platform.\r
+\r
+ ID: EArmObjPmcg\r
*/\r
typedef struct CmArmPmcgNode {\r
- /// An unique token used to ideintify this object\r
+ /// An unique token used to identify this object\r
CM_OBJECT_TOKEN Token;\r
/// Number of ID mappings\r
UINT32 IdMappingCount;\r
\r
/** A structure that describes the\r
ID Mappings for the Platform.\r
+\r
+ ID: EArmObjIdMappingArray\r
*/\r
typedef struct CmArmIdMapping {\r
/// Input base\r
\r
/** A structure that describes the\r
SMMU interrupts for the Platform.\r
+\r
+ ID: EArmObjSmmuInterruptArray\r
*/\r
typedef struct CmArmSmmuInterrupt {\r
/// Interrupt number\r
UINT32 Flags;\r
} CM_ARM_SMMU_INTERRUPT;\r
\r
+/** A structure that describes the Processor Hierarchy Node (Type 0) in PPTT\r
+\r
+ ID: EArmObjProcHierarchyInfo\r
+*/\r
+typedef struct CmArmProcHierarchyInfo {\r
+ /// A unique token used to identify this object\r
+ CM_OBJECT_TOKEN Token;\r
+ /// Processor structure flags (ACPI 6.3 - January 2019, PPTT, Table 5-155)\r
+ UINT32 Flags;\r
+ /// Token for the parent CM_ARM_PROC_HIERARCHY_INFO object in the processor\r
+ /// topology. A value of CM_NULL_TOKEN means this node has no parent.\r
+ CM_OBJECT_TOKEN ParentToken;\r
+ /// Token of the associated CM_ARM_GICC_INFO object which has the\r
+ /// corresponding ACPI Processor ID. A value of CM_NULL_TOKEN means this\r
+ /// node represents a group of associated processors and it does not have an\r
+ /// associated GIC CPU interface.\r
+ CM_OBJECT_TOKEN GicCToken;\r
+ /// Number of resources private to this Node\r
+ UINT32 NoOfPrivateResources;\r
+ /// Token of the array which contains references to the resources private to\r
+ /// this CM_ARM_PROC_HIERARCHY_INFO instance. This field is ignored if\r
+ /// the NoOfPrivateResources is 0, in which case it is recomended to set\r
+ /// this field to CM_NULL_TOKEN.\r
+ CM_OBJECT_TOKEN PrivateResourcesArrayToken;\r
+} CM_ARM_PROC_HIERARCHY_INFO;\r
+\r
+/** A structure that describes the Cache Type Structure (Type 1) in PPTT\r
+\r
+ ID: EArmObjCacheInfo\r
+*/\r
+typedef struct CmArmCacheInfo {\r
+ /// A unique token used to identify this object\r
+ CM_OBJECT_TOKEN Token;\r
+ /// Reference token for the next level of cache that is private to the same\r
+ /// CM_ARM_PROC_HIERARCHY_INFO instance. A value of CM_NULL_TOKEN means this\r
+ /// entry represents the last cache level appropriate to the processor\r
+ /// hierarchy node structures using this entry.\r
+ CM_OBJECT_TOKEN NextLevelOfCacheToken;\r
+ /// Size of the cache in bytes\r
+ UINT32 Size;\r
+ /// Number of sets in the cache\r
+ UINT32 NumberOfSets;\r
+ /// Integer number of ways. The maximum associativity supported by\r
+ /// ACPI Cache type structure is limited to MAX_UINT8. However,\r
+ /// the maximum number of ways supported by the architecture is\r
+ /// PPTT_ARM_CCIDX_CACHE_ASSOCIATIVITY_MAX. Therfore this field\r
+ /// is 32-bit wide.\r
+ UINT32 Associativity;\r
+ /// Cache attributes (ACPI 6.3 - January 2019, PPTT, Table 5-156)\r
+ UINT8 Attributes;\r
+ /// Line size in bytes\r
+ UINT16 LineSize;\r
+} CM_ARM_CACHE_INFO;\r
+\r
+/** A structure that describes the ID Structure (Type 2) in PPTT\r
+\r
+ ID: EArmObjProcNodeIdInfo\r
+*/\r
+typedef struct CmArmProcNodeIdInfo {\r
+ /// A unique token used to identify this object\r
+ CM_OBJECT_TOKEN Token;\r
+ // Vendor ID (as described in ACPI ID registry)\r
+ UINT32 VendorId;\r
+ /// First level unique node ID\r
+ UINT64 Level1Id;\r
+ /// Second level unique node ID\r
+ UINT64 Level2Id;\r
+ /// Major revision of the node\r
+ UINT16 MajorRev;\r
+ /// Minor revision of the node\r
+ UINT16 MinorRev;\r
+ /// Spin revision of the node\r
+ UINT16 SpinRev;\r
+} CM_ARM_PROC_NODE_ID_INFO;\r
+\r
+/** A structure that describes a reference to another Configuration Manager\r
+ object.\r
+\r
+ This is useful for creating an array of reference tokens. The framework\r
+ can then query the configuration manager for these arrays using the\r
+ object ID EArmObjCmRef.\r
+\r
+ This can be used is to represent one-to-many relationships between objects.\r
+\r
+ ID: EArmObjCmRef\r
+*/\r
+typedef struct CmArmObjRef {\r
+ /// Token of the CM object being referenced\r
+ CM_OBJECT_TOKEN ReferenceToken;\r
+} CM_ARM_OBJ_REF;\r
+\r
#pragma pack()\r
\r
#endif // ARM_NAMESPACE_OBJECTS_H_\r
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