+++ /dev/null
-/*++\r
-\r
-Copyright (c) 2004, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-\r
-Module Name:\r
-\r
- EfiRegTableLib.h\r
- \r
-Abstract: \r
-\r
- Definitions and macros for building register tables for chipset \r
- initialization..\r
- \r
- Components linking this lib must include CpuIo, PciRootBridgeIo, and \r
- BootScriptSave protocols in their DPX.\r
- \r
-Revision History:\r
-\r
---*/\r
-\r
-#ifndef EFI_REG_TABLE_H\r
-#define EFI_REG_TABLE_H\r
-\r
-#include "Tiano.h"\r
-#include "EfiScriptLib.h"\r
-#include EFI_PROTOCOL_CONSUMER (CpuIo)\r
-#include EFI_PROTOCOL_CONSUMER (PciRootBridgeIo)\r
-\r
-//\r
-// RegTable OpCodes are encoded as follows:\r
-//\r
-// |31----------------------------16|15---------8|7-------0|\r
-// \ \ \\r
-// \ \ \\r
-// 31:16 defined by Base OpCode---+ \ \\r
-// Opcode Flags---+ \\r
-// Base OpCode---+\r
-//\r
-#define OPCODE_BASE(OpCode) ((UINT8)((OpCode) & 0xFF))\r
-#define OPCODE_FLAGS(OpCode) ((UINT8)(((OpCode) >> 8) & 0xFF)) \r
-#define OPCODE_EXTRA_DATA(OpCode) ((UINT16)((OpCode) >> 16)) \r
-\r
-//\r
-// RegTable Base OpCodes\r
-//\r
-#define OP_TERMINATE_TABLE 0\r
-#define OP_MEM_WRITE 1\r
-#define OP_MEM_READ_MODIFY_WRITE 2\r
-#define OP_IO_WRITE 3\r
-#define OP_IO_READ_MODIFY_WRITE 4\r
-#define OP_PCI_WRITE 5\r
-#define OP_PCI_READ_MODIFY_WRITE 6\r
-#define OP_STALL 7\r
-\r
-//\r
-// RegTable OpCode Flags\r
-//\r
-#define OPCODE_FLAG_S3SAVE 1\r
-\r
-\r
-#define TERMINATE_TABLE { (UINT32) OP_TERMINATE_TABLE, (UINT32) 0, (UINT32) 0 }\r
-\r
-\r
-//\r
-// REG_TABLE_ENTRY_PCI_WRITE encodes the width in the upper bits of the OpCode\r
-// as one of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH values\r
-//\r
-typedef struct {\r
- UINT32 OpCode;\r
- UINT32 PciAddress;\r
- UINT32 Data;\r
-} EFI_REG_TABLE_PCI_WRITE;\r
-\r
-#define PCI_WRITE(Bus, Dev, Fnc, Reg, Width, Data, S3Flag) \\r
- { \\r
- (UINT32) (OP_PCI_WRITE | ((S3Flag) << 8) | ((Width) << 16)), \\r
- (UINT32) (EFI_PCI_ADDRESS ((Bus), (Dev), (Fnc), (Reg))), \\r
- (UINT32) (Data), \\r
- (UINT32) (0) \\r
- }\r
-\r
-typedef struct {\r
- UINT32 OpCode;\r
- UINT32 PciAddress;\r
- UINT32 OrMask;\r
- UINT32 AndMask;\r
-} EFI_REG_TABLE_PCI_READ_MODIFY_WRITE;\r
-\r
-#define PCI_READ_MODIFY_WRITE(Bus, Dev, Fnc, Reg, Width, OrMask, AndMask, S3Flag) \\r
- { \\r
- (UINT32) (OP_PCI_READ_MODIFY_WRITE | ((S3Flag) << 8) | ((Width) << 16)), \\r
- (UINT32) (EFI_PCI_ADDRESS ((Bus), (Dev), (Fnc), (Reg))), \\r
- (UINT32) (OrMask), \\r
- (UINT32) (AndMask) \\r
- }\r
-\r
-typedef struct {\r
- UINT32 OpCode;\r
- UINT32 MemAddress;\r
- UINT32 OrMask;\r
- UINT32 AndMask;\r
-} EFI_REG_TABLE_MEM_READ_MODIFY_WRITE;\r
-\r
-#define MEM_READ_MODIFY_WRITE(Address, Width, OrMask, AndMask, S3Flag) \\r
- { \\r
- (UINT32) (OP_MEM_READ_MODIFY_WRITE | ((S3Flag) << 8) | ((Width) << 16)), \\r
- (UINT32) (Address), \\r
- (UINT32) (OrMask), \\r
- (UINT32) (AndMask) \\r
- }\r
- \r
-typedef struct {\r
- UINT32 OpCode;\r
- UINT32 Field2;\r
- UINT32 Field3;\r
- UINT32 Field4;\r
-} EFI_REG_TABLE_GENERIC;\r
-\r
-typedef union {\r
- EFI_REG_TABLE_GENERIC Generic;\r
- EFI_REG_TABLE_PCI_WRITE PciWrite;\r
- EFI_REG_TABLE_PCI_READ_MODIFY_WRITE PciReadModifyWrite;\r
- EFI_REG_TABLE_MEM_READ_MODIFY_WRITE MemReadModifyWrite;\r
-} EFI_REG_TABLE;\r
-\r
-VOID\r
-ProcessRegTablePci (\r
- EFI_REG_TABLE * RegTableEntry,\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL * PciRootBridgeIo,\r
- EFI_CPU_IO_PROTOCOL * CpuIo\r
- )\r
-/*++\r
-\r
-Routine Description:\r
- Processes register table assuming which may contain PCI, IO, MEM, and STALL\r
- entries.\r
- \r
- No parameter checking is done so the caller must be careful about omitting\r
- values for PciRootBridgeIo or CpuIo parameters. If the regtable does\r
- not contain any PCI accesses, it is safe to omit the PciRootBridgeIo (supply\r
- NULL). If the regtable does not contain any IO or Mem entries, it is safe to\r
- omit the CpuIo (supply NULL).\r
- \r
- The RegTableEntry parameter is not checked, but is required.\r
- \r
- gBS is assumed to have been defined and is used when processing stalls.\r
- \r
- The function processes each entry sequentially until an OP_TERMINATE_TABLE\r
- entry is encountered.\r
-\r
-Arguments:\r
- RegTableEntry - A pointer to the register table to process\r
- \r
- PciRootBridgeIo - A pointer to the instance of PciRootBridgeIo that is used\r
- when processing PCI table entries\r
- \r
- CpuIo - A pointer to the instance of CpuIo that is used when processing IO and\r
- MEM table entries\r
-\r
-Returns:\r
- Nothing. \r
- \r
---*/\r
-;\r
-\r
-VOID\r
-ProcessRegTableCpu (\r
- EFI_REG_TABLE * RegTableEntry,\r
- EFI_CPU_IO_PROTOCOL * CpuIo\r
- )\r
-/*++\r
-\r
-Routine Description:\r
- Processes register table assuming which may contain IO, MEM, and STALL\r
- entries, but must NOT contain any PCI entries. Any PCI entries cause an\r
- ASSERT in a DEBUG build and are skipped in a free build.\r
- \r
- No parameter checking is done. Both RegTableEntry and CpuIo parameters are\r
- required.\r
- \r
- gBS is assumed to have been defined and is used when processing stalls.\r
-\r
- The function processes each entry sequentially until an OP_TERMINATE_TABLE\r
- entry is encountered.\r
-\r
-Arguments:\r
- RegTableEntry - A pointer to the register table to process\r
- \r
- CpuIo - A pointer to the instance of CpuIo that is used when processing IO and\r
- MEM table entries\r
-\r
-Returns:\r
- Nothing. \r
- \r
---*/\r
-;\r
-\r
-#endif\r
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