/*++\r
\r
-Copyright (c) 2006 - 2007, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2006 - 2007, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
Module Name:\r
\r
PciEnumeratorSupport.c\r
- \r
+\r
Abstract:\r
\r
PCI Bus Driver\r
//\r
// Read the Vendor Id register\r
//\r
- Status = PciRootBridgeIo->Pci.Read (\r
+ Status = PciRootBridgeIoRead (\r
PciRootBridgeIo,\r
+ NULL,\r
EfiPciWidthUint32,\r
Address,\r
1,\r
// Read the entire config header for the device\r
//\r
\r
- Status = PciRootBridgeIo->Pci.Read (\r
+ Status = PciRootBridgeIoRead (\r
PciRootBridgeIo,\r
+ NULL,\r
EfiPciWidthUint32,\r
Address,\r
sizeof (PCI_TYPE00) / sizeof (UINT32),\r
//\r
PciIo = &(PciIoDevice->PciIo);\r
\r
- Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x19, 1, &SecBus);\r
+ Status = PciIoRead (PciIo, EfiPciIoWidthUint8, 0x19, 1, &SecBus);\r
\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
- \r
+\r
//\r
// Get resource padding for PPB\r
//\r
Func\r
);\r
if ((PciIoDevice != NULL) && gFullEnumeration) {\r
- InitializeP2C (PciIoDevice); \r
+ InitializeP2C (PciIoDevice);\r
}\r
} else {\r
\r
if (!PciIoDevice) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
- \r
+\r
//\r
// Update the bar information for this PCI device so as to support some specific device\r
//\r
- UpdatePciInfo (PciIoDevice);\r
+ if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_ACPI_RESOURCE_SUPPORT) {\r
+ UpdatePciInfo (PciIoDevice);\r
+ }\r
\r
if (PciIoDevice->DevicePath == NULL) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
- \r
+\r
//\r
// Detect this function has option rom\r
//\r
ResetPowerManagementFeature (PciIoDevice);\r
\r
}\r
- \r
+\r
//\r
// Insert it into a global tree for future reference\r
//\r
if (!PciIoDevice) {\r
return NULL;\r
}\r
- \r
+\r
//\r
// Create a device path for this PCI device and store it into its private data\r
//\r
//\r
// Test whether it support 32 decode or not\r
//\r
- PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);\r
- PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Value);\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);\r
+ PciIoRead (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);\r
+ PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);\r
+ PciIoRead (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Value);\r
+ PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);\r
\r
if (Value) {\r
if (Value & 0x01) {\r
// Preserve the original value\r
//\r
\r
- PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);\r
+ PciIoRead (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);\r
\r
//\r
// Raise TPL to high level to disable timer interrupt while the BAR is probed\r
//\r
OldTpl = gBS->RaiseTPL (EFI_TPL_HIGH_LEVEL);\r
\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &gAllOne);\r
- PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &Value);\r
+ PciIoWrite (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &gAllOne);\r
+ PciIoRead (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &Value);\r
\r
//\r
// Write back the original value\r
//\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);\r
+ PciIoWrite (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);\r
\r
//\r
// Restore TPL to its original level\r
gBS->RestoreTPL (OldTpl);\r
\r
if (IS_PCI_BRIDGE (&PciIoDevice->Pci) || IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {\r
- \r
+\r
//\r
// Preserve the original value\r
//\r
/*++\r
\r
Routine Description:\r
- Set the supported or current attributes of a PCI device \r
+ Set the supported or current attributes of a PCI device\r
\r
Arguments:\r
PciIoDevice - Structure pointer for PCI device.\r
BridgeControl - Bridge control value for PPB or P2C.\r
Option - Make a choice of EFI_SET_SUPPORTS or EFI_SET_ATTRIBUTES.\r
\r
- Returns: \r
+ Returns:\r
\r
--*/\r
\r
\r
Routine Description:\r
\r
- \r
+\r
\r
Arguments:\r
- \r
- \r
+\r
+\r
Returns:\r
- \r
+\r
EFI_SUCCESS Always success\r
- \r
+\r
\r
--*/\r
{\r
\r
if (Option == EFI_SET_SUPPORTS) {\r
\r
- Attributes |= EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE | \r
+ Attributes |= EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE |\r
EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED |\r
EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE |\r
EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE |\r
/*++\r
\r
Routine Description:\r
- \r
+\r
Determine if the device can support Fast Back to Back attribute\r
\r
Arguments:\r
// Read the status register\r
//\r
PciIo = &PciIoDevice->PciIo;\r
- Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, StatusIndex, 1, &StatusRegister);\r
+ Status = PciIoRead (PciIo, EfiPciIoWidthUint16, StatusIndex, 1, &StatusRegister);\r
if (EFI_ERROR (Status)) {\r
return EFI_UNSUPPORTED;\r
}\r
- \r
+\r
//\r
// Check the Fast B2B bit\r
//\r
/*++\r
\r
Routine Description:\r
- \r
+\r
Process the option ROM for all the children of the specified parent PCI device.\r
It can only be used after the first full Option ROM process.\r
\r
/*++\r
\r
Routine Description:\r
- \r
+\r
Determine the related attributes of all devices under a Root Bridge\r
\r
Arguments:\r
return Status;\r
}\r
} else {\r
- \r
+\r
//\r
// Set the attributes to be checked for common PCI devices and PPB or P2C\r
// Since some devices only support part of them, it is better to set the\r
/*\r
if (IS_PCI_IDE(&PciIoDevice->Pci)) {\r
\r
- PciIo = &PciIoDevice->PciIo; \r
+ PciIo = &PciIoDevice->PciIo;\r
\r
- PciIo->Pci.Read (\r
- PciIo, \r
- EfiPciIoWidthUint8, \r
- 0x09, \r
- 1, \r
+ PciIoRead (\r
+ PciIo,\r
+ EfiPciIoWidthUint8,\r
+ 0x09,\r
+ 1,\r
&IdePI\r
);\r
- \r
+\r
//\r
// Set native mode if it can be supported\r
- // \r
+ //\r
IdePI |= (((IdePI & 0x0F) >> 1) & 0x05);\r
\r
- PciIo->Pci.Write (\r
- PciIo, \r
- EfiPciIoWidthUint8, \r
- 0x09, \r
- 1, \r
+ PciIoWrite (\r
+ PciIo,\r
+ EfiPciIoWidthUint8,\r
+ 0x09,\r
+ 1,\r
&IdePI\r
- ); \r
- \r
- } \r
+ );\r
+\r
+ }\r
*/\r
}\r
\r
if (IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {\r
FastB2BSupport = FALSE;\r
}\r
- \r
+\r
//\r
// For RootBridge, PPB , P2C, go recursively to traverse all its children\r
//\r
UINTN BarIndex;\r
UINTN BarEndIndex;\r
BOOLEAN SetFlag;\r
+ EFI_PCI_DEVICE_INFO PciDeviceInfo;\r
VOID *Configuration;\r
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r
\r
Configuration = NULL;\r
\r
- //\r
- // It can only be supported after the Incompatible PCI Device\r
- // Support Protocol has been installed\r
- //\r
- if (gEfiIncompatiblePciDeviceSupport == NULL) {\r
-\r
- Status = gBS->LocateProtocol (\r
- &gEfiIncompatiblePciDeviceSupportProtocolGuid,\r
- NULL,\r
- (VOID **) &gEfiIncompatiblePciDeviceSupport\r
- );\r
- if (EFI_ERROR (Status)) {\r
- return EFI_UNSUPPORTED;\r
- }\r
- }\r
- \r
//\r
// Check whether the device belongs to incompatible devices or not\r
// If it is , then get its special requirement in the ACPI table\r
//\r
- Status = gEfiIncompatiblePciDeviceSupport->CheckDevice (\r
- gEfiIncompatiblePciDeviceSupport,\r
- PciIoDevice->Pci.Hdr.VendorId,\r
- PciIoDevice->Pci.Hdr.DeviceId,\r
- PciIoDevice->Pci.Hdr.RevisionID,\r
- PciIoDevice->Pci.Device.SubsystemVendorID,\r
- PciIoDevice->Pci.Device.SubsystemID,\r
- &Configuration\r
- );\r
+ PciDeviceInfo.VendorID = PciIoDevice->Pci.Hdr.VendorId;\r
+ PciDeviceInfo.DeviceID = PciIoDevice->Pci.Hdr.DeviceId;\r
+ PciDeviceInfo.RevisionID = PciIoDevice->Pci.Hdr.RevisionID;\r
+ PciDeviceInfo.SubsystemVendorID = PciIoDevice->Pci.Device.SubsystemVendorID;\r
+ PciDeviceInfo.SubsystemID = PciIoDevice->Pci.Device.SubsystemID;\r
+\r
+ Status = PciResourceUpdateCheck (&PciDeviceInfo, &Configuration);\r
\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
- \r
+\r
//\r
// Update PCI device information from the ACPI table\r
//\r
SetFlag = FALSE;\r
switch (Ptr->ResType) {\r
case ACPI_ADDRESS_SPACE_TYPE_MEM:\r
- \r
+\r
//\r
// Make sure the bar is memory type\r
//\r
break;\r
\r
case ACPI_ADDRESS_SPACE_TYPE_IO:\r
- \r
+\r
//\r
// Make sure the bar is IO type\r
//\r
}\r
\r
if (SetFlag) {\r
- \r
+\r
//\r
// Update the new alignment for the device\r
//\r
//\r
// Check the validity of the parameter\r
//\r
- if (NewAlignment != PCI_BAR_EVEN_ALIGN && \r
+ if (NewAlignment != PCI_BAR_EVEN_ALIGN &&\r
NewAlignment != PCI_BAR_SQUAD_ALIGN &&\r
- NewAlignment != PCI_BAR_DQUAD_ALIGN ) { \r
+ NewAlignment != PCI_BAR_DQUAD_ALIGN ) {\r
*Alignment = NewAlignment;\r
return ;\r
}\r
OldAlignment = RShiftU64 (OldAlignment, 4);\r
ShiftBit += 4;\r
}\r
- \r
+\r
//\r
// Adjust the alignment to even, quad or double quad boundary\r
//\r
OldAlignment = OldAlignment + 8 - (OldAlignment & 0x07);\r
}\r
}\r
- \r
+\r
//\r
// Update the old value\r
//\r
for (Data = Value; Data != 0; Data >>= 1) {\r
Index ++;\r
}\r
- Value |= ((UINT32)(-1) << Index); \r
+ Value |= ((UINT32)(-1) << Index);\r
\r
//\r
// Calculate the size of 64bit bar\r
break;\r
}\r
}\r
- \r
+\r
//\r
// Check the length again so as to keep compatible with some special bars\r
//\r
PciIoDevice->PciBar[BarIndex].BaseAddress = 0;\r
PciIoDevice->PciBar[BarIndex].Alignment = 0;\r
}\r
- \r
+\r
//\r
// Increment number of bar\r
//\r
/*++\r
\r
Routine Description:\r
- \r
+\r
This routine is used to initialize the bar of a PCI device\r
It can be called typically when a device is going to be rejected\r
\r
// has not been alloacted\r
//\r
for (Offset = 0x10; Offset <= 0x24; Offset += sizeof (UINT32)) {\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllOne);\r
+ PciIoWrite (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllOne);\r
}\r
\r
return EFI_SUCCESS;\r
// Io32, pMem32, pMem64 to quiescent state\r
// Resource base all ones, Resource limit all zeros\r
//\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1D, 1, &gAllZero);\r
+ PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);\r
+ PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1D, 1, &gAllZero);\r
\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x20, 1, &gAllOne);\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x22, 1, &gAllZero);\r
+ PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x20, 1, &gAllOne);\r
+ PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x22, 1, &gAllZero);\r
\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x24, 1, &gAllOne);\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x26, 1, &gAllZero);\r
+ PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x24, 1, &gAllOne);\r
+ PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x26, 1, &gAllZero);\r
\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllOne);\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x2C, 1, &gAllZero);\r
+ PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllOne);\r
+ PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x2C, 1, &gAllZero);\r
\r
//\r
// don't support use io32 as for now\r
//\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x30, 1, &gAllOne);\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x32, 1, &gAllZero);\r
+ PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x30, 1, &gAllOne);\r
+ PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x32, 1, &gAllZero);\r
\r
//\r
// Force Interrupt line to zero for cards that come up randomly\r
//\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero);\r
+ PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero);\r
\r
return EFI_SUCCESS;\r
}\r
// Io32, pMem32, pMem64 to quiescent state(\r
// Resource base all ones, Resource limit all zeros\r
//\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x1c, 1, &gAllOne);\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x20, 1, &gAllZero);\r
+ PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x1c, 1, &gAllOne);\r
+ PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x20, 1, &gAllZero);\r
\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x24, 1, &gAllOne);\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllZero);\r
+ PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x24, 1, &gAllOne);\r
+ PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllZero);\r
\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x2c, 1, &gAllOne);\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x30, 1, &gAllZero);\r
+ PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x2c, 1, &gAllOne);\r
+ PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x30, 1, &gAllZero);\r
\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x34, 1, &gAllOne);\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x38, 1, &gAllZero);\r
+ PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x34, 1, &gAllOne);\r
+ PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x38, 1, &gAllZero);\r
\r
//\r
// Force Interrupt line to zero for cards that come up randomly\r
//\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero);\r
+ PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero);\r
return EFI_SUCCESS;\r
}\r
\r
\r
Routine Description:\r
\r
- This routine is used to enumerate entire pci bus system \r
+ This routine is used to enumerate entire pci bus system\r
in a given platform\r
\r
Arguments:\r
Descriptors++;\r
continue;\r
}\r
- \r
+\r
//\r
// Record the root bridge io protocol\r
//\r
);\r
\r
if (!EFI_ERROR (Status)) {\r
- \r
+\r
//\r
// Remove those PCI devices which are rejected when full enumeration\r
//\r
MinBus - The min bus.\r
MaxBus - The max bus.\r
BusRange - The bus range.\r
- \r
+\r
Returns:\r
- \r
+\r
Status Code.\r
\r
--*/\r
}\r
\r
if (TestValue & 0x01) {\r
- \r
+\r
//\r
// IO Bar\r
//\r
- \r
+\r
Mask = 0xFFFFFFFC;\r
TestValue = TestValue & Mask;\r
if ((TestValue != 0) && (TestValue == (OldValue & Mask))) {\r
}\r
\r
} else {\r
- \r
+\r
//\r
// Mem Bar\r
//\r
- \r
+\r
Mask = 0xFFFFFFF0;\r
TestValue = TestValue & Mask;\r
\r
if ((TestValue & 0x07) == 0x04) {\r
- \r
+\r
//\r
// Mem64 or PMem64\r
//\r
BarOffset += sizeof (UINT32);\r
if ((TestValue != 0) && (TestValue == (OldValue & Mask))) {\r
- \r
+\r
//\r
// Test its high 32-Bit BAR\r
//\r
- \r
+\r
Status = BarExisted (PciIoDevice, BarOffset, &TestValue, &OldValue);\r
if (TestValue == OldValue) {\r
return TRUE;\r
}\r
\r
} else {\r
- \r
+\r
//\r
// Mem32 or PMem32\r
//\r
EFI_STATUS Status;\r
PCI_TYPE00 Pci;\r
UINT8 Device;\r
- UINT32 Register; \r
+ UINT32 Register;\r
UINT8 Func;\r
UINT64 Address;\r
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
if (!EFI_ERROR (Status) && (IS_PCI_BRIDGE (&Pci))) {\r
Register = 0;\r
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);\r
- Status = PciRootBridgeIo->Pci.Read (\r
+ Status = PciRootBridgeIoRead (\r
PciRootBridgeIo,\r
- EfiPciWidthUint32, \r
+ &Pci,\r
+ EfiPciWidthUint32,\r
Address,\r
1,\r
&Register\r
// Reset register 18h, 19h, 1Ah on PCI Bridge\r
//\r
Register &= 0xFF000000;\r
- Status = PciRootBridgeIo->Pci.Write (\r
+ Status = PciRootBridgeIoWrite (\r
PciRootBridgeIo,\r
- EfiPciWidthUint32, \r
+ &Pci,\r
+ EfiPciWidthUint32,\r
Address,\r
1,\r
&Register\r
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