//++\r
-// Copyright (c) 2006, Intel Corporation \r
-// All rights reserved. This program and the accompanying materials \r
-// are licensed and made available under the terms and conditions of the BSD License \r
-// which accompanies this distribution. The full text of the license may be found at \r
-// http://opensource.org/licenses/bsd-license.php \r
+// Copyright (c) 2006, Intel Corporation\r
+// All rights reserved. This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
// \r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-// \r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
// Module Name:\r
//\r
// IpfCpuCore.s\r
// Abstract:\r
// IPF Specific assembly routines\r
//\r
-//-- \r
+//--\r
\r
.file "IpfCpuCore.s"\r
\r
#include "IpfMacro.i"\r
-#include "IpfCpuCore.i"\r
+#include "Ipf\IpfCpuCore.i"\r
\r
//----------------------------------------------------------------------------------\r
// This module supports terminating CAR (Cache As RAM) stage. It copies all the\r
NESTED_SETUP (4,2,0,0)\r
\r
// first save all stack registers in GPRs.\r
- mov r13 = in0;; // this is a pointer to the PLABEL of the continuation function. \r
+ mov r13 = in0;; // this is a pointer to the PLABEL of the continuation function.\r
ld8 r16 = [r13],8;; // r16 = address of continuation function from the PLABEL\r
ld8 gp = [r13];; // gp = gp of continuation function from the PLABEL\r
mov b1 = r16;;\r
\r
mov r8 = in3;; // new stack pointer.\r
\r
- // r8 has the sp, this is 128K stack size, from this we will reserve 16K for the bspstore \r
+ // r8 has the sp, this is 128K stack size, from this we will reserve 16K for the bspstore\r
movl r15 = PEI_BSP_STORE_SIZE;;\r
sub r8 = r8, r15;;\r
add r15 = (GuardBand),r8;; // some little buffer, now r15 will be our bspstore\r
mov r4 = r15\r
mov r7 = r8\r
mov r16 = r8;; // will be the new sp in uncache mode\r
- \r
+\r
\r
alloc r11=0,0,0,0;; // Set 0-size frame\r
flushrs;;\r
\r
- mov r21 = RSC_KERNEL_DISABLED;; // for rse disable \r
- mov ar.rsc = r21;; // turn off RSE \r
+ mov r21 = RSC_KERNEL_DISABLED;; // for rse disable\r
+ mov ar.rsc = r21;; // turn off RSE\r
\r
add sp = r0, r16 // transfer to the EFI stack\r
- mov ar.bspstore = r15 // switch to EFI BSP \r
- invala // change of ar.bspstore needs invala. \r
- \r
+ mov ar.bspstore = r15 // switch to EFI BSP\r
+ invala // change of ar.bspstore needs invala.\r
+\r
mov r19 = RSC_KERNEL_LAZ;; // RSC enabled, Lazy mode\r
- mov ar.rsc = r19;; // turn rse on, in kernel mode \r
- \r
+ mov ar.rsc = r19;; // turn rse on, in kernel mode\r
+\r
//-----------------------------------------------------------------------------------\r
// Save here the meaningful stuff for next few lines and then make the PAL call.\r
// Make PAL call to terminate the CAR status.\r
\r
mov r28=ar.k3;;\r
dep r2 = r28,r0,0,8;; // Extract Function bits from GR20.\r
- cmp.eq p6,p7 = RecoveryFn,r2;; // Is it Recovery check \r
+ cmp.eq p6,p7 = RecoveryFn,r2;; // Is it Recovery check\r
(p7) br.sptk.few DoneCARTermination; // if not, don't terminate car..\r
\r
TerminateCAR::\r
//\r
// dead loop if the PAL call failed, we have the CAR on but the stack is now pointing to memory\r
//\r
- (p7) br.sptk.few ReturnToPEIMain;; \r
+ (p7) br.sptk.few ReturnToPEIMain;;\r
//\r
- // PAL call successed,now the stack are in memory so come into cache mode \r
+ // PAL call successed,now the stack are in memory so come into cache mode\r
// instead of uncache mode\r
//\r
\r
alloc r11=0,0,0,0;; // Set 0-size frame\r
flushrs;;\r
- \r
- mov r21 = RSC_KERNEL_DISABLED;; // for rse disable \r
- mov ar.rsc = r21;; // turn off RSE \r
- \r
- dep r6 = 0,r6,63,1 // zero the bit 63 \r
- dep r7 = 0,r7,63,1 // zero the bit 63 \r
- dep r4 = 0,r4,63,1;; // zero the bit 63 \r
- add sp = r0, r7 // transfer to the EFI stack in cache mode \r
- mov ar.bspstore = r4 // switch to EFI BSP \r
- invala // change of ar.bspstore needs invala. \r
- \r
+\r
+ mov r21 = RSC_KERNEL_DISABLED;; // for rse disable\r
+ mov ar.rsc = r21;; // turn off RSE\r
+\r
+ dep r6 = 0,r6,63,1 // zero the bit 63\r
+ dep r7 = 0,r7,63,1 // zero the bit 63\r
+ dep r4 = 0,r4,63,1;; // zero the bit 63\r
+ add sp = r0, r7 // transfer to the EFI stack in cache mode\r
+ mov ar.bspstore = r4 // switch to EFI BSP\r
+ invala // change of ar.bspstore needs invala.\r
+\r
mov r19 = RSC_KERNEL_LAZ;; // RSC enabled, Lazy mode\r
mov ar.rsc = r19;; // turn rse on, in kernel mode\r
\r
#endif\r
\r
-DoneCARTermination:: \r
+DoneCARTermination::\r
\r
- // allocate a stack frame: \r
+ // allocate a stack frame:\r
alloc r11=0,2,2,0 ;; // alloc outs going to ensuing DXE IPL service\r
// on the new stack\r
mov out0 = r5;;\r
- mov out1 = r6;; \r
+ mov out1 = r6;;\r
\r
mov r16 = b1;;\r
mov b6 = r16;;\r
// This routine is called by all processors simultaneously, to get some hand-off\r
// status that has been captured by IPF dispatcher and recorded in kernel registers.\r
//\r
-// Arguments : \r
+// Arguments :\r
//\r
// On Entry : None.\r
//\r
// Return Value: Lid, R20Status.\r
-// \r
+//\r
//--\r
//----------------------------------------------------------------------------------\r
PROCEDURE_ENTRY (GetHandOffStatus)\r
- \r
+\r
NESTED_SETUP (0,2+0,0,0)\r
\r
mov r8 = ar.k6 // Health Status (Self test params)\r
mov r9 = ar.k4 // LID bits\r
mov r10 = ar.k3;; // SAL_E entry state\r
mov r11 = ar.k7 // Return address to PAL\r
- \r
+\r
NESTED_RETURN\r
PROCEDURE_EXIT (GetHandOffStatus)\r
//----------------------------------------------------------------------------------\r
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