UINT8 *Ptr;\r
UINT8 *ThunkBase;\r
UINT64 Addr;\r
- UINT64 Code[3]; // Code in a bundle\r
- UINT64 RegNum; // register number for MOVL\r
- UINT64 I; // bits of MOVL immediate data\r
- UINT64 Ic; // bits of MOVL immediate data\r
- UINT64 Imm5c; // bits of MOVL immediate data\r
- UINT64 Imm9d; // bits of MOVL immediate data\r
- UINT64 Imm7b; // bits of MOVL immediate data\r
- UINT64 Br; // branch register for loading and jumping\r
+ UINT64 Code[3]; // Code in a bundle\r
+ UINT64 RegNum; // register number for MOVL\r
+ UINT64 I; // bits of MOVL immediate data\r
+ UINT64 Ic; // bits of MOVL immediate data\r
+ UINT64 Imm5c; // bits of MOVL immediate data\r
+ UINT64 Imm9d; // bits of MOVL immediate data\r
+ UINT64 Imm7b; // bits of MOVL immediate data\r
+ UINT64 Br; // branch register for loading and jumping\r
UINT64 *Data64Ptr;\r
UINT32 ThunkSize;\r
UINT32 Size;\r
//\r
// Next is simply Addr[62:22] (41 bits) of the address\r
//\r
- Code[1] = RightShiftU64 (Addr, 22) & 0x1ffffffffff;\r
+ Code[1] = RShiftU64 (Addr, 22) & 0x1ffffffffff;\r
\r
//\r
// Extract bits from the address for insertion into the instruction\r
// i = Addr[63:63]\r
//\r
- I = RightShiftU64 (Addr, 63) & 0x01;\r
+ I = RShiftU64 (Addr, 63) & 0x01;\r
//\r
// ic = Addr[21:21]\r
//\r
- Ic = RightShiftU64 (Addr, 21) & 0x01;\r
+ Ic = RShiftU64 (Addr, 21) & 0x01;\r
//\r
// imm5c = Addr[20:16] for 5 bits\r
//\r
- Imm5c = RightShiftU64 (Addr, 16) & 0x1F;\r
+ Imm5c = RShiftU64 (Addr, 16) & 0x1F;\r
//\r
// imm9d = Addr[15:7] for 9 bits\r
//\r
- Imm9d = RightShiftU64 (Addr, 7) & 0x1FF;\r
+ Imm9d = RShiftU64 (Addr, 7) & 0x1FF;\r
//\r
// imm7b = Addr[6:0] for 7 bits\r
//\r
//\r
// Next is jumbled data, including opcode and rest of address\r
//\r
- Code[2] = LeftShiftU64 (Imm7b, 13)\r
- | LeftShiftU64 (0x00, 20) // vc\r
- | LeftShiftU64 (Ic, 21)\r
- | LeftShiftU64 (Imm5c, 22)\r
- | LeftShiftU64 (Imm9d, 27)\r
- | LeftShiftU64 (I, 36)\r
- | LeftShiftU64 ((UINT64)MOVL_OPCODE, 37)\r
- | LeftShiftU64 ((RegNum & 0x7F), 6);\r
+ Code[2] = LShiftU64 (Imm7b, 13)\r
+ | LShiftU64 (0x00, 20) // vc\r
+ | LShiftU64 (Ic, 21)\r
+ | LShiftU64 (Imm5c, 22)\r
+ | LShiftU64 (Imm9d, 27)\r
+ | LShiftU64 (I, 36)\r
+ | LShiftU64 ((UINT64)MOVL_OPCODE, 37)\r
+ | LShiftU64 ((RegNum & 0x7F), 6);\r
\r
WriteBundle ((VOID *) Ptr, 0x05, Code[0], Code[1], Code[2]);\r
\r
//\r
// Next is simply Addr[62:22] (41 bits) of the address\r
//\r
- Code[1] = RightShiftU64 (Addr, 22) & 0x1ffffffffff;\r
+ Code[1] = RShiftU64 (Addr, 22) & 0x1ffffffffff;\r
\r
//\r
// Extract bits from the address for insertion into the instruction\r
// i = Addr[63:63]\r
//\r
- I = RightShiftU64 (Addr, 63) & 0x01;\r
+ I = RShiftU64 (Addr, 63) & 0x01;\r
//\r
// ic = Addr[21:21]\r
//\r
- Ic = RightShiftU64 (Addr, 21) & 0x01;\r
+ Ic = RShiftU64 (Addr, 21) & 0x01;\r
//\r
// imm5c = Addr[20:16] for 5 bits\r
//\r
- Imm5c = RightShiftU64 (Addr, 16) & 0x1F;\r
+ Imm5c = RShiftU64 (Addr, 16) & 0x1F;\r
//\r
// imm9d = Addr[15:7] for 9 bits\r
//\r
- Imm9d = RightShiftU64 (Addr, 7) & 0x1FF;\r
+ Imm9d = RShiftU64 (Addr, 7) & 0x1FF;\r
//\r
// imm7b = Addr[6:0] for 7 bits\r
//\r
//\r
// Next is jumbled data, including opcode and rest of address\r
//\r
- Code[2] = LeftShiftU64 (Imm7b, 13)\r
- | LeftShiftU64 (0x00, 20) // vc\r
- | LeftShiftU64 (Ic, 21)\r
- | LeftShiftU64 (Imm5c, 22)\r
- | LeftShiftU64 (Imm9d, 27)\r
- | LeftShiftU64 (I, 36)\r
- | LeftShiftU64 ((UINT64)MOVL_OPCODE, 37)\r
- | LeftShiftU64 ((RegNum & 0x7F), 6);\r
+ Code[2] = LShiftU64 (Imm7b, 13)\r
+ | LShiftU64 (0x00, 20) // vc\r
+ | LShiftU64 (Ic, 21)\r
+ | LShiftU64 (Imm5c, 22)\r
+ | LShiftU64 (Imm9d, 27)\r
+ | LShiftU64 (I, 36)\r
+ | LShiftU64 ((UINT64)MOVL_OPCODE, 37)\r
+ | LShiftU64 ((RegNum & 0x7F), 6);\r
\r
WriteBundle ((VOID *) Ptr, 0x05, Code[0], Code[1], Code[2]);\r
\r
//\r
// Next is simply Addr[62:22] (41 bits) of the address\r
//\r
- Code[1] = RightShiftU64 (Addr, 22) & 0x1ffffffffff;\r
+ Code[1] = RShiftU64 (Addr, 22) & 0x1ffffffffff;\r
\r
//\r
// Extract bits from the address for insertion into the instruction\r
// i = Addr[63:63]\r
//\r
- I = RightShiftU64 (Addr, 63) & 0x01;\r
+ I = RShiftU64 (Addr, 63) & 0x01;\r
//\r
// ic = Addr[21:21]\r
//\r
- Ic = RightShiftU64 (Addr, 21) & 0x01;\r
+ Ic = RShiftU64 (Addr, 21) & 0x01;\r
//\r
// imm5c = Addr[20:16] for 5 bits\r
//\r
- Imm5c = RightShiftU64 (Addr, 16) & 0x1F;\r
+ Imm5c = RShiftU64 (Addr, 16) & 0x1F;\r
//\r
// imm9d = Addr[15:7] for 9 bits\r
//\r
- Imm9d = RightShiftU64 (Addr, 7) & 0x1FF;\r
+ Imm9d = RShiftU64 (Addr, 7) & 0x1FF;\r
//\r
// imm7b = Addr[6:0] for 7 bits\r
//\r
//\r
// Next is jumbled data, including opcode and rest of address\r
//\r
- Code[2] = LeftShiftU64(Imm7b, 13)\r
- | LeftShiftU64 (0x00, 20) // vc\r
- | LeftShiftU64 (Ic, 21)\r
- | LeftShiftU64 (Imm5c, 22)\r
- | LeftShiftU64 (Imm9d, 27)\r
- | LeftShiftU64 (I, 36)\r
- | LeftShiftU64 ((UINT64)MOVL_OPCODE, 37)\r
- | LeftShiftU64 ((RegNum & 0x7F), 6);\r
+ Code[2] = LShiftU64(Imm7b, 13)\r
+ | LShiftU64 (0x00, 20) // vc\r
+ | LShiftU64 (Ic, 21)\r
+ | LShiftU64 (Imm5c, 22)\r
+ | LShiftU64 (Imm9d, 27)\r
+ | LShiftU64 (I, 36)\r
+ | LShiftU64 ((UINT64)MOVL_OPCODE, 37)\r
+ | LShiftU64 ((RegNum & 0x7F), 6);\r
\r
WriteBundle ((VOID *) Ptr, 0x05, Code[0], Code[1], Code[2]);\r
\r
// register and user register (same user register as previous bundle).\r
//\r
Br = 6;\r
- Code[2] |= LeftShiftU64 (Br, 6);\r
- Code[2] |= LeftShiftU64 (RegNum, 13);\r
+ Code[2] |= LShiftU64 (Br, 6);\r
+ Code[2] |= LShiftU64 (RegNum, 13);\r
WriteBundle ((VOID *) Ptr, 0x0d, Code[0], Code[1], Code[2]);\r
\r
//\r
Code[0] = OPCODE_NOP;\r
Code[1] = OPCODE_NOP;\r
Code[2] = OPCODE_BR_COND_SPTK_FEW;\r
- Code[2] |= LeftShiftU64 (Br, 13);\r
+ Code[2] |= LShiftU64 (Br, 13);\r
WriteBundle ((VOID *) Ptr, 0x1d, Code[0], Code[1], Code[2]);\r
\r
//\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- Low64 = LeftShiftU64 (Slot1, 46) | LeftShiftU64 (Slot0, 5) | Template;\r
- High64 = RightShiftU64 (Slot1, 18) | LeftShiftU64 (Slot2, 23);\r
+ Low64 = LShiftU64 (Slot1, 46) | LShiftU64 (Slot0, 5) | Template;\r
+ High64 = RShiftU64 (Slot1, 18) | LShiftU64 (Slot2, 23);\r
\r
//\r
// Now write it all out\r
BPtr = (UINT8 *) MemPtr;\r
for (Index = 0; Index < 8; Index++) {\r
*BPtr = (UINT8) Low64;\r
- Low64 = RightShiftU64 (Low64, 8);\r
+ Low64 = RShiftU64 (Low64, 8);\r
BPtr++;\r
}\r
\r
for (Index = 0; Index < 8; Index++) {\r
*BPtr = (UINT8) High64;\r
- High64 = RightShiftU64 (High64, 8);\r
+ High64 = RShiftU64 (High64, 8);\r
BPtr++;\r
}\r
\r
goto Action;\r
}\r
\r
- CodeOne18 = RightShiftU64 (*((UINT64 *)CalleeAddr + 2), 46) & 0x3FFFF;\r
+ CodeOne18 = RShiftU64 (*((UINT64 *)CalleeAddr + 2), 46) & 0x3FFFF;\r
CodeOne23 = (*((UINT64 *)CalleeAddr + 3)) & 0x7FFFFF;\r
- CodeTwoI = RightShiftU64 (*((UINT64 *)CalleeAddr + 3), 59) & 0x1;\r
- CodeTwoIc = RightShiftU64 (*((UINT64 *)CalleeAddr + 3), 44) & 0x1;\r
- CodeTwo7b = RightShiftU64 (*((UINT64 *)CalleeAddr + 3), 36) & 0x7F;\r
- CodeTwo5c = RightShiftU64 (*((UINT64 *)CalleeAddr + 3), 45) & 0x1F;\r
- CodeTwo9d = RightShiftU64 (*((UINT64 *)CalleeAddr + 3), 50) & 0x1FF;\r
+ CodeTwoI = RShiftU64 (*((UINT64 *)CalleeAddr + 3), 59) & 0x1;\r
+ CodeTwoIc = RShiftU64 (*((UINT64 *)CalleeAddr + 3), 44) & 0x1;\r
+ CodeTwo7b = RShiftU64 (*((UINT64 *)CalleeAddr + 3), 36) & 0x7F;\r
+ CodeTwo5c = RShiftU64 (*((UINT64 *)CalleeAddr + 3), 45) & 0x1F;\r
+ CodeTwo9d = RShiftU64 (*((UINT64 *)CalleeAddr + 3), 50) & 0x1FF;\r
\r
TargetEbcAddr = CodeTwo7b\r
- | LeftShiftU64 (CodeTwo9d, 7)\r
- | LeftShiftU64 (CodeTwo5c, 16)\r
- | LeftShiftU64 (CodeTwoIc, 21)\r
- | LeftShiftU64 (CodeOne18, 22)\r
- | LeftShiftU64 (CodeOne23, 40)\r
- | LeftShiftU64 (CodeTwoI, 63)\r
+ | LShiftU64 (CodeTwo9d, 7)\r
+ | LShiftU64 (CodeTwo5c, 16)\r
+ | LShiftU64 (CodeTwoIc, 21)\r
+ | LShiftU64 (CodeOne18, 22)\r
+ | LShiftU64 (CodeOne23, 40)\r
+ | LShiftU64 (CodeTwoI, 63)\r
;\r
\r
Action:\r