+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2014-2017, Linaro Limited. All rights reserved.\r
-*\r
-* SPDX-License-Identifier: BSD-2-Clause-Patent\r
-*\r
-**/\r
-\r
-\r
-#ifndef __DWEMMC_H__\r
-#define __DWEMMC_H__\r
-\r
-#include <Protocol/EmbeddedGpio.h>\r
-\r
-// DW MMC Registers\r
-#define DWEMMC_CTRL ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x000)\r
-#define DWEMMC_PWREN ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x004)\r
-#define DWEMMC_CLKDIV ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x008)\r
-#define DWEMMC_CLKSRC ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x00c)\r
-#define DWEMMC_CLKENA ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x010)\r
-#define DWEMMC_TMOUT ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x014)\r
-#define DWEMMC_CTYPE ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x018)\r
-#define DWEMMC_BLKSIZ ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x01c)\r
-#define DWEMMC_BYTCNT ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x020)\r
-#define DWEMMC_INTMASK ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x024)\r
-#define DWEMMC_CMDARG ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x028)\r
-#define DWEMMC_CMD ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x02c)\r
-#define DWEMMC_RESP0 ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x030)\r
-#define DWEMMC_RESP1 ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x034)\r
-#define DWEMMC_RESP2 ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x038)\r
-#define DWEMMC_RESP3 ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x03c)\r
-#define DWEMMC_RINTSTS ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x044)\r
-#define DWEMMC_STATUS ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x048)\r
-#define DWEMMC_FIFOTH ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x04c)\r
-#define DWEMMC_TCBCNT ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x05c)\r
-#define DWEMMC_TBBCNT ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x060)\r
-#define DWEMMC_DEBNCE ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x064)\r
-#define DWEMMC_HCON ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x070)\r
-#define DWEMMC_UHSREG ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x074)\r
-#define DWEMMC_BMOD ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x080)\r
-#define DWEMMC_DBADDR ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x088)\r
-#define DWEMMC_IDSTS ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x08c)\r
-#define DWEMMC_IDINTEN ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x090)\r
-#define DWEMMC_DSCADDR ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x094)\r
-#define DWEMMC_BUFADDR ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x098)\r
-#define DWEMMC_CARDTHRCTL ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0X100)\r
-#define DWEMMC_DATA ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0X200)\r
-\r
-#define CMD_UPDATE_CLK 0x80202000\r
-#define CMD_START_BIT (1 << 31)\r
-\r
-#define MMC_8BIT_MODE (1 << 16)\r
-\r
-#define BIT_CMD_RESPONSE_EXPECT (1 << 6)\r
-#define BIT_CMD_LONG_RESPONSE (1 << 7)\r
-#define BIT_CMD_CHECK_RESPONSE_CRC (1 << 8)\r
-#define BIT_CMD_DATA_EXPECTED (1 << 9)\r
-#define BIT_CMD_READ (0 << 10)\r
-#define BIT_CMD_WRITE (1 << 10)\r
-#define BIT_CMD_BLOCK_TRANSFER (0 << 11)\r
-#define BIT_CMD_STREAM_TRANSFER (1 << 11)\r
-#define BIT_CMD_SEND_AUTO_STOP (1 << 12)\r
-#define BIT_CMD_WAIT_PRVDATA_COMPLETE (1 << 13)\r
-#define BIT_CMD_STOP_ABORT_CMD (1 << 14)\r
-#define BIT_CMD_SEND_INIT (1 << 15)\r
-#define BIT_CMD_UPDATE_CLOCK_ONLY (1 << 21)\r
-#define BIT_CMD_READ_CEATA_DEVICE (1 << 22)\r
-#define BIT_CMD_CCS_EXPECTED (1 << 23)\r
-#define BIT_CMD_ENABLE_BOOT (1 << 24)\r
-#define BIT_CMD_EXPECT_BOOT_ACK (1 << 25)\r
-#define BIT_CMD_DISABLE_BOOT (1 << 26)\r
-#define BIT_CMD_MANDATORY_BOOT (0 << 27)\r
-#define BIT_CMD_ALTERNATE_BOOT (1 << 27)\r
-#define BIT_CMD_VOLT_SWITCH (1 << 28)\r
-#define BIT_CMD_USE_HOLD_REG (1 << 29)\r
-#define BIT_CMD_START (1 << 31)\r
-\r
-#define DWEMMC_INT_EBE (1 << 15) /* End-bit Err */\r
-#define DWEMMC_INT_SBE (1 << 13) /* Start-bit Err */\r
-#define DWEMMC_INT_HLE (1 << 12) /* Hardware-lock Err */\r
-#define DWEMMC_INT_FRUN (1 << 11) /* FIFO UN/OV RUN */\r
-#define DWEMMC_INT_DRT (1 << 9) /* Data timeout */\r
-#define DWEMMC_INT_RTO (1 << 8) /* Response timeout */\r
-#define DWEMMC_INT_DCRC (1 << 7) /* Data CRC err */\r
-#define DWEMMC_INT_RCRC (1 << 6) /* Response CRC err */\r
-#define DWEMMC_INT_RXDR (1 << 5)\r
-#define DWEMMC_INT_TXDR (1 << 4)\r
-#define DWEMMC_INT_DTO (1 << 3) /* Data trans over */\r
-#define DWEMMC_INT_CMD_DONE (1 << 2)\r
-#define DWEMMC_INT_RE (1 << 1)\r
-\r
-#define DWEMMC_IDMAC_DES0_DIC (1 << 1)\r
-#define DWEMMC_IDMAC_DES0_LD (1 << 2)\r
-#define DWEMMC_IDMAC_DES0_FS (1 << 3)\r
-#define DWEMMC_IDMAC_DES0_CH (1 << 4)\r
-#define DWEMMC_IDMAC_DES0_ER (1 << 5)\r
-#define DWEMMC_IDMAC_DES0_CES (1 << 30)\r
-#define DWEMMC_IDMAC_DES0_OWN (1 << 31)\r
-#define DWEMMC_IDMAC_DES1_BS1(x) ((x) & 0x1fff)\r
-#define DWEMMC_IDMAC_DES2_BS2(x) (((x) & 0x1fff) << 13)\r
-#define DWEMMC_IDMAC_SWRESET (1 << 0)\r
-#define DWEMMC_IDMAC_FB (1 << 1)\r
-#define DWEMMC_IDMAC_ENABLE (1 << 7)\r
-\r
-#define EMMC_FIX_RCA 6\r
-\r
-/* bits in MMC0_CTRL */\r
-#define DWEMMC_CTRL_RESET (1 << 0)\r
-#define DWEMMC_CTRL_FIFO_RESET (1 << 1)\r
-#define DWEMMC_CTRL_DMA_RESET (1 << 2)\r
-#define DWEMMC_CTRL_INT_EN (1 << 4)\r
-#define DWEMMC_CTRL_DMA_EN (1 << 5)\r
-#define DWEMMC_CTRL_IDMAC_EN (1 << 25)\r
-#define DWEMMC_CTRL_RESET_ALL (DWEMMC_CTRL_RESET | DWEMMC_CTRL_FIFO_RESET | DWEMMC_CTRL_DMA_RESET)\r
-\r
-#define DWEMMC_STS_DATA_BUSY (1 << 9)\r
-\r
-#define DWEMMC_FIFO_TWMARK(x) (x & 0xfff)\r
-#define DWEMMC_FIFO_RWMARK(x) ((x & 0x1ff) << 16)\r
-#define DWEMMC_DMA_BURST_SIZE(x) ((x & 0x7) << 28)\r
-\r
-#define DWEMMC_CARD_RD_THR(x) ((x & 0xfff) << 16)\r
-#define DWEMMC_CARD_RD_THR_EN (1 << 0)\r
-\r
-#define DWEMMC_GET_HDATA_WIDTH(x) (((x) >> 7) & 0x7)\r
-\r
-#endif // __DWEMMC_H__\r
projects / mirror_edk2.git / blobdiff