EmbeddedPkg/Lan9118Dxe: add LAN9118 MMIO wrappers

[mirror_edk2.git] / EmbeddedPkg / Drivers / Lan9118Dxe / Lan9118DxeUtil.c

diff --git a/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.c b/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.c
index bd20eebd042dd1fe9a0b591fc57350b43362c29c..002ea203ae56ba728a9ee992498047b827299f12 100644 (file)
--- a/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.c
+++ b/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.c
@@ -115,6 +115,54 @@ IndirectMACRead32 (
   return MmioRead32 (LAN9118_MAC_CSR_DATA);\r
 }\r
 \r
+/*\r
+ * LAN9118 chips have special restrictions on some back-to-back Write/Read or\r
+ * Read/Read pairs of accesses. After a read or write that changes the state of\r
+ * the device, there is a period in which stale values may be returned in\r
+ * response to a read. This period is dependent on the registers accessed.\r
+ *\r
+ * We must delay prior reads by this period. This can either be achieved by\r
+ * timer-based delays, or by performing dummy reads of the BYTE_TEST register,\r
+ * for which the recommended number of reads is described in the LAN9118 data\r
+ * sheet. This is required in addition to any memory barriers.\r
+ *\r
+ * This function performs a number of dummy reads of the BYTE_TEST register, as\r
+ * a building block for the above.\r
+ */\r
+VOID\r
+WaitDummyReads (\r
+  UINTN Count\r
+  )\r
+{\r
+       while (Count--)\r
+         MmioRead32(LAN9118_BYTE_TEST);\r
+}\r
+\r
+UINT32\r
+Lan9118RawMmioRead32(\r
+  UINTN Address,\r
+  UINTN Delay\r
+  )\r
+{\r
+  UINT32 Value;\r
+\r
+  Value = MmioRead32(Address);\r
+  WaitDummyReads(Delay);\r
+  return Value;\r
+}\r
+\r
+UINT32\r
+Lan9118RawMmioWrite32(\r
+  UINTN Address,\r
+  UINT32 Value,\r
+  UINTN Delay\r
+  )\r
+{\r
+  MmioWrite32(Address, Value);\r
+  WaitDummyReads(Delay);\r
+  return Value;\r
+}\r
+\r
 // Function to write to MAC indirect registers\r
 UINT32\r
 IndirectMACWrite32 (\r