--- /dev/null
+/** @file\r
+* SMSC LAN91x series Network Controller Driver.\r
+*\r
+* Copyright (c) 2013-2017 Linaro.org\r
+*\r
+* This program and the accompanying materials are licensed and\r
+* made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license\r
+* may be found at: http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#ifndef __LAN91XDXEHW_H__\r
+#define __LAN91XDXEHW_H__\r
+\r
+#include <Base.h>\r
+\r
+#define MakeRegister(Bank, Offset) (((Bank) << 8) | (Offset))\r
+#define RegisterToBank(Register) (((Register) >> 8) & 0x07)\r
+#define RegisterToOffset(Register) ((Register) & 0x0f)\r
+\r
+/*---------------------------------------------------------------------------------------------------------------------\r
+\r
+ SMSC LAN91x Registers\r
+\r
+---------------------------------------------------------------------------------------------------------------------*/\r
+#define LAN91X_BANK_OFFSET 0xe // Bank Select Register (all banks)\r
+\r
+#define LAN91X_TCR MakeRegister (0, 0x0) // Transmit Control Register\r
+#define LAN91X_EPHSR MakeRegister (0, 0x2) // EPH Status Register\r
+#define LAN91X_RCR MakeRegister (0, 0x4) // Receive Control Register\r
+#define LAN91X_ECR MakeRegister (0, 0x6) // Counter Register\r
+#define LAN91X_MIR MakeRegister (0, 0x8) // Memory Information Register\r
+#define LAN91X_RPCR MakeRegister (0, 0xa) // Receive/Phy Control Register\r
+\r
+#define LAN91X_CR MakeRegister (1, 0x0) // Configuration Register\r
+#define LAN91X_BAR MakeRegister (1, 0x2) // Base Address Register\r
+#define LAN91X_IAR0 MakeRegister (1, 0x4) // Individual Address Register 0\r
+#define LAN91X_IAR1 MakeRegister (1, 0x5) // Individual Address Register 1\r
+#define LAN91X_IAR2 MakeRegister (1, 0x6) // Individual Address Register 2\r
+#define LAN91X_IAR3 MakeRegister (1, 0x7) // Individual Address Register 3\r
+#define LAN91X_IAR4 MakeRegister (1, 0x8) // Individual Address Register 4\r
+#define LAN91X_IAR5 MakeRegister (1, 0x9) // Individual Address Register 5\r
+#define LAN91X_GPR MakeRegister (1, 0xa) // General Purpose Register\r
+#define LAN91X_CTR MakeRegister (1, 0xc) // Control Register\r
+\r
+#define LAN91X_MMUCR MakeRegister (2, 0x0) // MMU Command Register\r
+#define LAN91X_PNR MakeRegister (2, 0x2) // Packet Number Register\r
+#define LAN91X_ARR MakeRegister (2, 0x3) // Allocation Result Register\r
+#define LAN91X_FIFO MakeRegister (2, 0x4) // FIFO Ports Register\r
+#define LAN91X_PTR MakeRegister (2, 0x6) // Pointer Register\r
+#define LAN91X_DATA0 MakeRegister (2, 0x8) // Data Register 0\r
+#define LAN91X_DATA1 MakeRegister (2, 0x9) // Data Register 1\r
+#define LAN91X_DATA2 MakeRegister (2, 0xa) // Data Register 2\r
+#define LAN91X_DATA3 MakeRegister (2, 0xb) // Data Register 3\r
+#define LAN91X_IST MakeRegister (2, 0xc) // Interrupt Status Register\r
+#define LAN91X_MSK MakeRegister (2, 0xd) // Interrupt Mask Register\r
+\r
+#define LAN91X_MT0 MakeRegister (3, 0x0) // Multicast Table Register 0\r
+#define LAN91X_MT1 MakeRegister (3, 0x1) // Multicast Table Register 1\r
+#define LAN91X_MT2 MakeRegister (3, 0x2) // Multicast Table Register 2\r
+#define LAN91X_MT3 MakeRegister (3, 0x3) // Multicast Table Register 3\r
+#define LAN91X_MT4 MakeRegister (3, 0x4) // Multicast Table Register 4\r
+#define LAN91X_MT5 MakeRegister (3, 0x5) // Multicast Table Register 5\r
+#define LAN91X_MT6 MakeRegister (3, 0x6) // Multicast Table Register 6\r
+#define LAN91X_MT7 MakeRegister (3, 0x7) // Multicast Table Register 7\r
+#define LAN91X_MGMT MakeRegister (3, 0x8) // Management Interface Register\r
+#define LAN91X_REV MakeRegister (3, 0xa) // Revision Register\r
+#define LAN91X_RCV MakeRegister (3, 0xc) // RCV Register\r
+\r
+// Transmit Control Register Bits\r
+#define TCR_TXENA BIT0\r
+#define TCR_LOOP BIT1\r
+#define TCR_FORCOL BIT2\r
+#define TCR_PAD_EN BIT7\r
+#define TCR_NOCRC BIT8\r
+#define TCR_MON_CSN BIT10\r
+#define TCR_FDUPLX BIT11\r
+#define TCR_STP_SQET BIT12\r
+#define TCR_EPH_LOOP BIT13\r
+#define TCR_SWFDUP BIT15\r
+\r
+#define TCR_DEFAULT (TCR_TXENA | TCR_PAD_EN)\r
+#define TCR_CLEAR 0x0\r
+\r
+// EPH Status Register Bits\r
+#define EPHSR_TX_SUC BIT0\r
+#define EPHSR_SNGLCOL BIT1\r
+#define EPHSR_MULCOL BIT2\r
+#define EPHSR_LTX_MULT BIT3\r
+#define EPHSR_16COL BIT4\r
+#define EPHSR_SQET BIT5\r
+#define EPHSR_LTX_BRD BIT6\r
+#define EPHSR_TX_DEFR BIT7\r
+#define EPHSR_LATCOL BIT9\r
+#define EPHSR_LOST_CARR BIT10\r
+#define EPHSR_EXC_DEF BIT11\r
+#define EPHSR_CTR_ROL BIT12\r
+#define EPHSR_LINK_OK BIT14\r
+\r
+// Receive Control Register Bits\r
+#define RCR_RX_ABORT BIT0\r
+#define RCR_PRMS BIT1\r
+#define RCR_ALMUL BIT2\r
+#define RCR_RXEN BIT8\r
+#define RCR_STRIP_CRC BIT9\r
+#define RCR_ABORT_ENB BIT13\r
+#define RCR_FILT_CAR BIT14\r
+#define RCR_SOFT_RST BIT15\r
+\r
+#define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)\r
+#define RCR_CLEAR 0x0\r
+\r
+// Receive/Phy Control Register Bits\r
+#define RPCR_LS0B BIT2\r
+#define RPCR_LS1B BIT3\r
+#define RPCR_LS2B BIT4\r
+#define RPCR_LS0A BIT5\r
+#define RPCR_LS1A BIT6\r
+#define RPCR_LS2A BIT7\r
+#define RPCR_ANEG BIT11\r
+#define RPCR_DPLX BIT12\r
+#define RPCR_SPEED BIT13\r
+\r
+// Configuration Register Bits\r
+#define CR_EXT_PHY BIT9\r
+#define CR_GPCNTRL BIT10\r
+#define CR_NO_WAIT BIT12\r
+#define CR_EPH_POWER_EN BIT15\r
+\r
+#define CR_DEFAULT (CR_EPH_POWER_EN | CR_NO_WAIT)\r
+\r
+// Control Register Bits\r
+#define CTR_STORE BIT0\r
+#define CTR_RELOAD BIT1\r
+#define CTR_EEPROM_SEL BIT2\r
+#define CTR_TE_ENABLE BIT5\r
+#define CTR_CR_ENABLE BIT6\r
+#define CTR_LE_ENABLE BIT7\r
+#define CTR_AUTO_REL BIT11\r
+#define CTR_RCV_BAD BIT14\r
+\r
+#define CTR_RESERVED (BIT12 | BIT9 | BIT4)\r
+#define CTR_DEFAULT (CTR_RESERVED | CTR_AUTO_REL)\r
+\r
+// MMU Command Register Bits\r
+#define MMUCR_BUSY BIT0\r
+\r
+// MMU Command Register Operaction Codes\r
+#define MMUCR_OP_NOOP (0 << 5) // No operation\r
+#define MMUCR_OP_TX_ALLOC (1 << 5) // Allocate memory for TX\r
+#define MMUCR_OP_RESET_MMU (2 << 5) // Reset MMU to initial state\r
+#define MMUCR_OP_RX_POP (3 << 5) // Remove frame from top of RX FIFO\r
+#define MMUCR_OP_RX_POP_REL (4 << 5) // Remove and release frame from top of RX FIFO\r
+#define MMUCR_OP_RX_REL (5 << 5) // Release specific RX frame\r
+#define MMUCR_OP_TX_PUSH (6 << 5) // Enqueue packet number into TX FIFO\r
+#define MMUCR_OP_TX_RESET (7 << 5) // Reset TX FIFOs\r
+\r
+// Packet Number Register Bits\r
+#define PNR_PACKET (0x3f)\r
+\r
+// Allocation Result Register Bits\r
+#define ARR_PACKET (0x3f)\r
+#define ARR_FAILED BIT7\r
+\r
+// FIFO Ports Register Bits\r
+#define FIFO_TX_PACKET (0x003f)\r
+#define FIFO_TEMPTY BIT7\r
+#define FIFO_RX_PACKET (0x3f00)\r
+#define FIFO_REMPTY BIT15\r
+\r
+// Pointer Register Bits\r
+#define PTR_POINTER (0x07ff)\r
+#define PTR_NOT_EMPTY BIT11\r
+#define PTR_READ BIT13\r
+#define PTR_AUTO_INCR BIT14\r
+#define PTR_RCV BIT15\r
+\r
+// Interupt Status and Mask Register Bits\r
+#define IST_RCV BIT0\r
+#define IST_TX BIT1\r
+#define IST_TX_EMPTY BIT2\r
+#define IST_ALLOC BIT3\r
+#define IST_RX_OVRN BIT4\r
+#define IST_EPH BIT5\r
+#define IST_MD BIT7\r
+\r
+// Management Interface\r
+#define MGMT_MDO BIT0\r
+#define MGMT_MDI BIT1\r
+#define MGMT_MCLK BIT2\r
+#define MGMT_MDOE BIT3\r
+#define MGMT_MSK_CRS100 BIT14\r
+\r
+// RCV Register\r
+#define RCV_MBO (0x1f)\r
+#define RCV_RCV_DISCRD BIT7\r
+\r
+// Packet RX Status word bits\r
+#define RX_MULTICAST BIT0\r
+#define RX_HASH (0x7e)\r
+#define RX_TOO_SHORT BIT10\r
+#define RX_TOO_LONG BIT11\r
+#define RX_ODD_FRAME BIT12\r
+#define RX_BAD_CRC BIT13\r
+#define RX_BROADCAST BIT14\r
+#define RX_ALGN_ERR BIT15\r
+\r
+// Packet Byte Count word bits\r
+#define BCW_COUNT (0x7fe)\r
+\r
+// Packet Control Word bits\r
+#define PCW_ODD_BYTE (0x00ff)\r
+#define PCW_CRC BIT12\r
+#define PCW_ODD BIT13\r
+\r
+/*---------------------------------------------------------------------------------------------------------------------\r
+\r
+ SMSC PHY Registers\r
+\r
+ Most of these should be common, as there is\r
+ documented STANDARD for PHY registers!\r
+\r
+---------------------------------------------------------------------------------------------------------------------*/\r
+//\r
+// PHY Register Numbers\r
+//\r
+#define PHY_INDEX_BASIC_CTRL 0\r
+#define PHY_INDEX_BASIC_STATUS 1\r
+#define PHY_INDEX_ID1 2\r
+#define PHY_INDEX_ID2 3\r
+#define PHY_INDEX_AUTO_NEG_ADVERT 4\r
+#define PHY_INDEX_AUTO_NEG_LINK_ABILITY 5\r
+\r
+#define PHY_INDEX_CONFIG1 16\r
+#define PHY_INDEX_CONFIG2 17\r
+#define PHY_INDEX_STATUS_OUTPUT 18\r
+#define PHY_INDEX_MASK 19\r
+\r
+\r
+// PHY control register bits\r
+#define PHYCR_COLL_TEST BIT7 // Collision test enable\r
+#define PHYCR_DUPLEX_MODE BIT8 // Set Duplex Mode\r
+#define PHYCR_RST_AUTO BIT9 // Restart Auto-Negotiation of Link abilities\r
+#define PHYCR_PD BIT11 // Power-Down switch\r
+#define PHYCR_AUTO_EN BIT12 // Auto-Negotiation Enable\r
+#define PHYCR_SPEED_SEL BIT13 // Link Speed Selection\r
+#define PHYCR_LOOPBK BIT14 // Set loopback mode\r
+#define PHYCR_RESET BIT15 // Do a PHY reset\r
+\r
+// PHY status register bits\r
+#define PHYSTS_EXT_CAP BIT0 // Extended Capabilities Register capability\r
+#define PHYSTS_JABBER BIT1 // Jabber condition detected\r
+#define PHYSTS_LINK_STS BIT2 // Link Status\r
+#define PHYSTS_AUTO_CAP BIT3 // Auto-Negotiation Capability\r
+#define PHYSTS_REMOTE_FAULT BIT4 // Remote fault detected\r
+#define PHYSTS_AUTO_COMP BIT5 // Auto-Negotiation Completed\r
+#define PHYSTS_10BASET_HDPLX BIT11 // 10Mbps Half-Duplex ability\r
+#define PHYSTS_10BASET_FDPLX BIT12 // 10Mbps Full-Duplex ability\r
+#define PHYSTS_100BASETX_HDPLX BIT13 // 100Mbps Half-Duplex ability\r
+#define PHYSTS_100BASETX_FDPLX BIT14 // 100Mbps Full-Duplex ability\r
+#define PHYSTS_100BASE_T4 BIT15 // Base T4 ability\r
+\r
+// PHY Auto-Negotiation advertisement\r
+#define PHYANA_SEL_MASK ((UINT32)0x1F) // Link type selector\r
+#define PHYANA_CSMA BIT0 // Advertise CSMA capability\r
+#define PHYANA_10BASET BIT5 // Advertise 10BASET capability\r
+#define PHYANA_10BASETFD BIT6 // Advertise 10BASET Full duplex capability\r
+#define PHYANA_100BASETX BIT7 // Advertise 100BASETX capability\r
+#define PHYANA_100BASETXFD BIT8 // Advertise 100 BASETX Full duplex capability\r
+#define PHYANA_100BASET4 BIT9 // Advertise 100 BASETX Full duplex capability\r
+#define PHYANA_PAUSE_OP_MASK (3 << 10) // Advertise PAUSE frame capability\r
+#define PHYANA_REMOTE_FAULT BIT13 // Remote fault detected\r
+\r
+#endif /* __LAN91XDXEHW_H__ */\r
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