+++ /dev/null
-/** @file\r
-Definition of FDC registers and structures.\r
-\r
-Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
-\r
-SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
-**/\r
-\r
-#ifndef _PEI_RECOVERY_FDC_H_\r
-#define _PEI_RECOVERY_FDC_H_\r
-\r
-//\r
-// FDC Registers\r
-//\r
-#define FDC_REGISTER_DOR 2 //Digital Output Register\r
-#define FDC_REGISTER_MSR 4 //Main Status Register\r
-#define FDC_REGISTER_DTR 5 //Data Register\r
-#define FDC_REGISTER_CCR 7 //Configuration Control Register(data rate select)\r
-#define FDC_REGISTER_DIR 7 //Digital Input Register(diskchange)\r
-//\r
-// FDC Register Bit Definitions\r
-//\r
-//\r
-// Digital Out Register(WO)\r
-//\r
-#define SELECT_DRV BIT0 // Select Drive: 0=A 1=B\r
-#define RESET_FDC BIT2 // Reset FDC\r
-#define INT_DMA_ENABLE BIT3 // Enable Int & DMA\r
-#define DRVA_MOTOR_ON BIT4 // Turn On Drive A Motor\r
-#define DRVB_MOTOR_ON BIT5 // Turn On Drive B Motor\r
-//\r
-// Main Status Register(RO)\r
-//\r
-#define MSR_DAB BIT0 // Drive A Busy\r
-#define MSR_DBB BIT1 // Drive B Busy\r
-#define MSR_CB BIT4 // FDC Busy\r
-#define MSR_NDM BIT5 // Non-DMA Mode\r
-#define MSR_DIO BIT6 // Data Input/Output\r
-#define MSR_RQM BIT7 // Request For Master\r
-//\r
-// Configuration Control Register(WO)\r
-//\r
-#define CCR_DRC (BIT0 | BIT1) // Data Rate select\r
-//\r
-// Digital Input Register(RO)\r
-//\r
-#define DIR_DCL BIT7 // Disk change line\r
-#define DRC_500KBS 0x0 // 500K\r
-#define DRC_300KBS 0x01 // 300K\r
-#define DRC_250KBS 0x02 // 250K\r
-//\r
-// FDC Command Code\r
-//\r
-#define READ_DATA_CMD 0x06\r
-#define SEEK_CMD 0x0F\r
-#define RECALIBRATE_CMD 0x07\r
-#define SENSE_INT_STATUS_CMD 0x08\r
-#define SPECIFY_CMD 0x03\r
-#define SENSE_DRV_STATUS_CMD 0x04\r
-\r
-///\r
-/// CMD_MT: Multi_Track Selector\r
-/// when set , this flag selects the multi-track operating mode.\r
-/// In this mode, the FDC treats a complete cylinder under head0 and 1 as a single track\r
-///\r
-#define CMD_MT BIT7\r
-\r
-///\r
-/// CMD_MFM: MFM/FM Mode Selector\r
-/// A one selects the double density(MFM) mode\r
-/// A zero selects single density (FM) mode\r
-///\r
-#define CMD_MFM BIT6\r
-\r
-///\r
-/// CMD_SK: Skip Flag\r
-/// When set to 1, sectors containing a deleted data address mark will automatically be skipped\r
-/// during the execution of Read Data.\r
-/// When set to 0, the sector is read or written the same as the read and write commands.\r
-///\r
-#define CMD_SK BIT5\r
-\r
-//\r
-// FDC Status Register Bit Definitions\r
-//\r
-//\r
-// Status Register 0\r
-//\r
-#define STS0_IC (BIT7 | BIT6) // Interrupt Code\r
-#define STS0_SE BIT5 // Seek End: the FDC completed a seek or recalibrate command\r
-#define STS0_EC BIT4 // Equipment Check\r
-#define STS0_NR BIT3 // Not Ready(unused), this bit is always 0\r
-#define STS0_HA BIT2 // Head Address: the current head address\r
-//\r
-// STS0_US1 & STS0_US0: Drive Select(the current selected drive)\r
-//\r
-#define STS0_US1 BIT1 // Unit Select1\r
-#define STS0_US0 BIT0 // Unit Select0\r
-//\r
-// Status Register 1\r
-//\r
-#define STS1_EN BIT7 // End of Cylinder\r
-//\r
-// BIT6 is unused\r
-//\r
-#define STS1_DE BIT5 // Data Error: The FDC detected a CRC error in either the ID field or data field of a sector\r
-#define STS1_OR BIT4 // Overrun/Underrun: Becomes set if FDC does not receive CPU or DMA service within the required time interval\r
-//\r
-// BIT3 is unused\r
-//\r
-#define STS1_ND BIT2 // No data\r
-#define STS1_NW BIT1 // Not Writable\r
-#define STS1_MA BIT0 // Missing Address Mark\r
-\r
-//\r
-// Status Register 2\r
-//\r
-// BIT7 is unused\r
-//\r
-#define STS2_CM BIT6 // Control Mark\r
-#define STS2_DD BIT5 // Data Error in Data Field: The FDC detected a CRC error in the data field\r
-#define STS2_WC BIT4 // Wrong Cylinder: The track address from sector ID field is different from the track address maintained inside FDC\r
-//\r
-// BIT3 is unused\r
-// BIT2 is unused\r
-//\r
-#define STS2_BC BIT1 // Bad Cylinder\r
-#define STS2_MD BIT0 // Missing Address Mark in DataField\r
-\r
-//\r
-// Status Register 3\r
-//\r
-// BIT7 is unused\r
-//\r
-#define STS3_WP BIT6 // Write Protected\r
-//\r
-// BIT5 is unused\r
-//\r
-#define STS3_T0 BIT4 // Track 0\r
-//\r
-// BIT3 is unused\r
-//\r
-#define STS3_HD BIT2 // Head Address\r
-//\r
-// STS3_US1 & STS3_US0 : Drive Select\r
-//\r
-#define STS3_US1 BIT1 // Unit Select1\r
-#define STS3_US0 BIT0 // Unit Select0\r
-\r
-//\r
-// Status Register 0 Interrupt Code Description\r
-//\r
-#define IC_NT 0x0 // Normal Termination of Command\r
-#define IC_AT 0x40 // Abnormal Termination of Command\r
-#define IC_IC 0x80 // Invalid Command\r
-#define IC_ATRC 0xC0 // Abnormal Termination caused by Polling\r
-\r
-///\r
-/// Table of parameters for diskette\r
-///\r
-typedef struct {\r
- UINT8 EndOfTrack; ///< End of track\r
- UINT8 GapLength; ///< Gap length\r
- UINT8 DataLength; ///< Data length\r
- UINT8 Number; ///< Number of bytes per sector\r
- UINT8 MaxTrackNum;\r
- UINT8 MotorStartTime;\r
- UINT8 MotorOffTime;\r
- UINT8 HeadSettlingTime;\r
- UINT8 DataTransferRate;\r
-} DISKET_PARA_TABLE;\r
-\r
-///\r
-/// Structure for FDC Command Packet 1\r
-///\r
-typedef struct {\r
- UINT8 CommandCode;\r
- UINT8 DiskHeadSel;\r
- UINT8 Cylinder;\r
- UINT8 Head;\r
- UINT8 Sector;\r
- UINT8 Number;\r
- UINT8 EndOfTrack;\r
- UINT8 GapLength;\r
- UINT8 DataLength;\r
-} FDC_COMMAND_PACKET1;\r
-\r
-///\r
-/// Structure for FDC Command Packet 2\r
-///\r
-typedef struct {\r
- UINT8 CommandCode;\r
- UINT8 DiskHeadSel;\r
-} FDC_COMMAND_PACKET2;\r
-\r
-///\r
-/// Structure for FDC Specify Command\r
-///\r
-typedef struct {\r
- UINT8 CommandCode;\r
- UINT8 SrtHut;\r
- UINT8 HltNd;\r
-} FDC_SPECIFY_CMD;\r
-\r
-///\r
-/// Structure for FDC Seek Command\r
-///\r
-typedef struct {\r
- UINT8 CommandCode;\r
- UINT8 DiskHeadSel;\r
- UINT8 NewCylinder;\r
-} FDC_SEEK_CMD;\r
-\r
-///\r
-/// Structure for FDC Result Packet\r
-///\r
-typedef struct {\r
- UINT8 Status0;\r
- UINT8 Status1;\r
- UINT8 Status2;\r
- UINT8 CylinderNumber;\r
- UINT8 HeaderAddress;\r
- UINT8 Record;\r
- UINT8 Number;\r
-} FDC_RESULT_PACKET;\r
-\r
-#endif\r
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