#ifndef _IDE_DATA_H\r
#define _IDE_DATA_H\r
\r
-//\r
-// bit definition\r
-//\r
-#define bit0 (1 << 0)\r
-#define bit1 (1 << 1)\r
-#define bit2 (1 << 2)\r
-#define bit3 (1 << 3)\r
-#define bit4 (1 << 4)\r
-#define bit5 (1 << 5)\r
-#define bit6 (1 << 6)\r
-#define bit7 (1 << 7)\r
-#define bit8 (1 << 8)\r
-#define bit9 (1 << 9)\r
-#define bit10 (1 << 10)\r
-#define bit11 (1 << 11)\r
-#define bit12 (1 << 12)\r
-#define bit13 (1 << 13)\r
-#define bit14 (1 << 14)\r
-#define bit15 (1 << 15)\r
-#define bit16 (1 << 16)\r
-#define bit17 (1 << 17)\r
-#define bit18 (1 << 18)\r
-#define bit19 (1 << 19)\r
-#define bit20 (1 << 20)\r
-#define bit21 (1 << 21)\r
-#define bit22 (1 << 22)\r
-#define bit23 (1 << 23)\r
-#define bit24 (1 << 24)\r
-#define bit25 (1 << 25)\r
-#define bit26 (1 << 26)\r
-#define bit27 (1 << 27)\r
-#define bit28 (1 << 28)\r
-#define bit29 (1 << 29)\r
-#define bit30 (1 << 30)\r
-#define bit31 (1 << 31)\r
+#include <IndustryStandard/Atapi.h>\r
\r
//\r
// common constants\r
// Bit definitions in Programming Interface byte of the Class Code field\r
// in PCI IDE controller's Configuration Space\r
//\r
-#define IDE_PRIMARY_OPERATING_MODE bit0\r
-#define IDE_PRIMARY_PROGRAMMABLE_INDICATOR bit1\r
-#define IDE_SECONDARY_OPERATING_MODE bit2\r
-#define IDE_SECONDARY_PROGRAMMABLE_INDICATOR bit3\r
-\r
-//\r
-// IDE registers bit definitions\r
-//\r
-\r
-//\r
-// Err Reg\r
-//\r
-#define BBK_ERR bit7 /* Bad block detected */\r
-#define UNC_ERR bit6 /* Uncorrectable Data */\r
-#define MC_ERR bit5 /* Media Change */\r
-#define IDNF_ERR bit4 /* ID Not Found */\r
-#define MCR_ERR bit3 /* Media Change Requested */\r
-#define ABRT_ERR bit2 /* Aborted Command */\r
-#define TK0NF_ERR bit1 /* Track 0 Not Found */\r
-#define AMNF_ERR bit0 /* Address Mark Not Found */\r
+#define IDE_PRIMARY_OPERATING_MODE BIT0\r
+#define IDE_PRIMARY_PROGRAMMABLE_INDICATOR BIT1\r
+#define IDE_SECONDARY_OPERATING_MODE BIT2\r
+#define IDE_SECONDARY_PROGRAMMABLE_INDICATOR BIT3\r
\r
-//\r
-// Device/Head Reg\r
-//\r
-#define LBA_MODE bit6\r
-#define DEV bit4\r
-#define HS3 bit3\r
-#define HS2 bit2\r
-#define HS1 bit1\r
-#define HS0 bit0\r
-#define CHS_MODE (0)\r
-#define DRV0 (0)\r
-#define DRV1 (1)\r
-#define MST_DRV DRV0\r
-#define SLV_DRV DRV1\r
-\r
-//\r
-// Status Reg\r
-//\r
-#define BSY bit7 /* Controller Busy */\r
-#define DRDY bit6 /* Drive Ready */\r
-#define DWF bit5 /* Drive Write Fault */\r
-#define DSC bit4 /* Disk Seek Complete */\r
-#define DRQ bit3 /* Data Request */\r
-#define CORR bit2 /* Corrected Data */\r
-#define IDX bit1 /* Index */\r
-#define ERR bit0 /* Error */\r
-\r
-//\r
-// Device Control Reg\r
-//\r
-#define SRST bit2 /* Software Reset */\r
-#define IEN_L bit1 /* Interrupt Enable #*/\r
\r
//\r
// Bus Master Reg\r
//\r
-#define BMIC_nREAD bit3\r
-#define BMIC_START bit0\r
-#define BMIS_INTERRUPT bit2\r
-#define BMIS_ERROR bit1\r
+#define BMIC_nREAD BIT3\r
+#define BMIC_START BIT0\r
+#define BMIS_INTERRUPT BIT2\r
+#define BMIS_ERROR BIT1\r
\r
#define BMICP_OFFSET 0x00\r
#define BMISP_OFFSET 0x02\r
//\r
#define ATASMARTTIMEOUT 10000\r
\r
-//\r
-// ATA Commands Code\r
-//\r
-#define ATA_INITIALIZE_DEVICE 0x91\r
-\r
-//\r
-// Class 1\r
-//\r
-#define IDENTIFY_DRIVE_CMD 0xec\r
-#define READ_BUFFER_CMD 0xe4\r
-#define READ_SECTORS_CMD 0x20\r
-#define READ_SECTORS_WITH_RETRY_CMD 0x21\r
-#define READ_LONG_CMD 0x22\r
-#define READ_LONG_WITH_RETRY_CMD 0x23\r
-//\r
-// Class 1 - Atapi6 enhanced commands\r
-//\r
-#define READ_SECTORS_EXT_CMD 0x24\r
-\r
-//\r
-// Class 2\r
-//\r
-#define FORMAT_TRACK_CMD 0x50\r
-#define WRITE_BUFFER_CMD 0xe8\r
-#define WRITE_SECTORS_CMD 0x30\r
-#define WRITE_SECTORS_WITH_RETRY_CMD 0x31\r
-#define WRITE_LONG_CMD 0x32\r
-#define WRITE_LONG_WITH_RETRY_CMD 0x33\r
-#define WRITE_VERIFY_CMD 0x3c\r
-//\r
-// Class 2 - Atapi6 enhanced commands\r
-//\r
-#define WRITE_SECTORS_EXT_CMD 0x34\r
-\r
-//\r
-// Class 3\r
-//\r
-#define ACK_MEDIA_CHANGE_CMD 0xdb\r
-#define BOOT_POST_BOOT_CMD 0xdc\r
-#define BOOT_PRE_BOOT_CMD 0xdd\r
-#define CHECK_POWER_MODE_CMD 0x98\r
-#define CHECK_POWER_MODE_CMD_ALIAS 0xe5\r
-#define DOOR_LOCK_CMD 0xde\r
-#define DOOR_UNLOCK_CMD 0xdf\r
-#define EXEC_DRIVE_DIAG_CMD 0x90\r
-#define IDLE_CMD_ALIAS 0x97\r
-#define IDLE_CMD 0xe3\r
-#define IDLE_IMMEDIATE_CMD 0x95\r
-#define IDLE_IMMEDIATE_CMD_ALIAS 0xe1\r
-#define INIT_DRIVE_PARAM_CMD 0x91\r
-#define RECALIBRATE_CMD 0x10 /* aliased to 1x */\r
-#define READ_DRIVE_STATE_CMD 0xe9\r
-#define SET_MULTIPLE_MODE_CMD 0xC6\r
-#define READ_DRIVE_STATE_CMD 0xe9\r
-#define READ_VERIFY_CMD 0x40\r
-#define READ_VERIFY_WITH_RETRY_CMD 0x41\r
-#define SEEK_CMD 0x70 /* aliased to 7x */\r
-#define SET_FEATURES_CMD 0xef\r
-#define STANDBY_CMD 0x96\r
-#define STANDBY_CMD_ALIAS 0xe2\r
-#define STANDBY_IMMEDIATE_CMD 0x94\r
-#define STANDBY_IMMEDIATE_CMD_ALIAS 0xe0\r
-\r
-//\r
-// Class 4\r
-//\r
-#define READ_DMA_CMD 0xc8\r
-#define READ_DMA_WITH_RETRY_CMD 0xc9\r
-#define READ_DMA_EXT_CMD 0x25\r
-#define WRITE_DMA_CMD 0xca\r
-#define WRITE_DMA_WITH_RETRY_CMD 0xcb\r
-#define WRITE_DMA_EXT_CMD 0x35\r
-\r
-//\r
-// Class 5\r
-//\r
-#define READ_MULTIPLE_CMD 0xc4\r
-#define REST_CMD 0xe7\r
-#define RESTORE_DRIVE_STATE_CMD 0xea\r
-#define SET_SLEEP_MODE_CMD 0x99\r
-#define SET_SLEEP_MODE_CMD_ALIAS 0xe6\r
-#define WRITE_MULTIPLE_CMD 0xc5\r
-#define WRITE_SAME_CMD 0xe9\r
-\r
-//\r
-// Class 6 - Host protected area access feature set\r
-//\r
-#define READ_NATIVE_MAX_ADDRESS_CMD 0xf8\r
-#define SET_MAX_ADDRESS_CMD 0xf9\r
-\r
-//\r
-// Class 6 - ATA/ATAPI-6 enhanced commands\r
-//\r
-#define READ_NATIVE_MAX_ADDRESS_EXT_CMD 0x27\r
-#define SET_MAX_ADDRESS_CMD_EXT 0x37\r
-\r
-//\r
-// Class 6 - SET_MAX related sub command (in feature register)\r
-//\r
-#define PARTIES_SET_MAX_ADDRESS_SUB_CMD 0x00\r
-#define PARTIES_SET_PASSWORD_SUB_CMD 0x01\r
-#define PARTIES_LOCK_SUB_CMD 0x02\r
-#define PARTIES_UNLOCK_SUB_CMD 0x03\r
-#define PARTIES_FREEZE_SUB_CMD 0x04\r
-\r
-//\r
-// S.M.A.R.T\r
-//\r
-#define ATA_SMART_CMD 0xb0\r
-#define ATA_CONSTANT_C2 0xc2\r
-#define ATA_CONSTANT_4F 0x4f\r
-#define ATA_SMART_ENABLE_OPERATION 0xd8\r
-#define ATA_SMART_RETURN_STATUS 0xda\r
-\r
-//\r
-// Error codes for Exec Drive Diag\r
-//\r
-#define DRIV_DIAG_NO_ERROR (0x01)\r
-#define DRIV_DIAG_FORMATTER_ERROR (0x02)\r
-#define DRIV_DIAG_DATA_BUFFER_ERROR (0x03)\r
-#define DRIV_DIAG_ECC_CKT_ERRROR (0x04)\r
-#define DRIV_DIAG_UP_ERROR (0x05)\r
-#define DRIV_DIAG_SLAVE_DRV_ERROR (0x80) /* aliased to 0x8x */\r
-\r
-//\r
-// Codes for Format Track\r
-//\r
-#define FORMAT_GOOD_SECTOR (0x00)\r
-#define FORMAT_SUSPEND_ALLOC (0x01)\r
-#define FORMAT_REALLOC_SECTOR (0x02)\r
-#define FORMAT_MARK_SECTOR_DEFECTIVE (0x03)\r
-\r
-//\r
-// IDE_IDENTIFY bits\r
-// config bits :\r
-//\r
-#define ID_CONFIG_RESERVED0 bit0\r
-#define ID_CONFIG_HARD_SECTORED_DRIVE bit1\r
-#define ID_CONFIG_SOFT_SECTORED_DRIVE bit2\r
-#define ID_CONFIG_NON_MFM bit3\r
-#define ID_CONFIG_15uS_HEAD_SWITCHING bit4\r
-#define ID_CONFIG_SPINDLE_MOTOR_CONTROL bit5\r
-#define ID_CONFIG_HARD_DRIVE bit6\r
-#define ID_CONFIG_CHANGEABLE_MEDIUM bit7\r
-#define ID_CONFIG_DATA_RATE_TO_5MHZ bit8\r
-#define ID_CONFIG_DATA_RATE_5_TO_10MHZ bit9\r
-#define ID_CONFIG_DATA_RATE_ABOVE_10MHZ bit10\r
-#define ID_CONFIG_MOTOR_SPEED_TOLERANCE_ABOVE_0_5_PERC bit11\r
-#define ID_CONFIG_DATA_CLK_OFFSET_AVAIL bit12\r
-#define ID_CONFIG_TRACK_OFFSET_AVAIL bit13\r
-#define ID_CONFIG_SPEED_TOLERANCE_GAP_NECESSARY bit14\r
-#define ID_CONFIG_RESERVED1 bit15\r
-\r
-#define ID_DOUBLE_WORD_IO_POSSIBLE bit01\r
-#define ID_LBA_SUPPORTED bit9\r
-#define ID_DMA_SUPPORTED bit8\r
-\r
-#define SET_FEATURE_ENABLE_8BIT_TRANSFER (0x01)\r
-#define SET_FEATURE_ENABLE_WRITE_CACHE (0x02)\r
-#define SET_FEATURE_TRANSFER_MODE (0x03)\r
-#define SET_FEATURE_WRITE_SAME_WRITE_SPECIFIC_AREA (0x22)\r
-#define SET_FEATURE_DISABLE_RETRIES (0x33)\r
-//\r
-// for Read & Write Longs\r
-//\r
-#define SET_FEATURE_VENDOR_SPEC_ECC_LENGTH (0x44)\r
-#define SET_FEATURE_PLACE_NO_OF_CACHE_SEGMENTS_IN_SECTOR_NO_REG (0x54)\r
-#define SET_FEATURE_DISABLE_READ_AHEAD (0x55)\r
-#define SET_FEATURE_MAINTAIN_PARAM_AFTER_RESET (0x66)\r
-#define SET_FEATURE_DISABLE_ECC (0x77)\r
-#define SET_FEATURE_DISABLE_8BIT_TRANSFER (0x81)\r
-#define SET_FEATURE_DISABLE_WRITE_CACHE (0x82)\r
-#define SET_FEATURE_ENABLE_ECC (0x88)\r
-#define SET_FEATURE_ENABLE_RETRIES (0x99)\r
-#define SET_FEATURE_ENABLE_READ_AHEAD (0xaa)\r
-#define SET_FEATURE_SET_SECTOR_CNT_REG_AS_NO_OF_READ_AHEAD_SECTORS (0xab)\r
-#define SET_FEATURE_ALLOW_REST_MODE (0xac)\r
-//\r
-// for Read & Write Longs\r
-//\r
-#define SET_FEATURE_4BYTE_ECC (0xbb)\r
-#define SET_FEATURE_DEFALUT_FEATURES_ON_SOFTWARE_RESET (0xcc)\r
-#define SET_FEATURE_WRITE_SAME_TO_WRITE_ENTIRE_MEDIUM (0xdd)\r
-\r
-#define BLOCK_TRANSFER_MODE (0x00)\r
-#define SINGLE_WORD_DMA_TRANSFER_MODE (0x10)\r
-#define MULTI_WORD_DMA_TRANSFER_MODE (0x20)\r
-#define TRANSFER_MODE_MASK (0x07) // 3 LSBs\r
-\r
-//\r
-// Drive 0 - Head 0\r
-//\r
-#define DEFAULT_DRIVE (0x00)\r
-#define DEFAULT_CMD (0xa0)\r
-//\r
-// default content of device control register, disable INT\r
-//\r
-#define DEFAULT_CTL (0x0a)\r
-#define DEFAULT_IDE_BM_IO_BASE_ADR (0xffa0)\r
\r
//\r
// ATAPI6 related data structure definition\r
//\r
#define MAX_28BIT_ADDRESSING_CAPACITY 0xfffffff\r
\r
-//\r
-// Move the IDENTIFY section to DXE\Protocol\IdeControllerInit\r
-//\r
-\r
-//\r
-// ATAPI Command\r
-//\r
-#define ATAPI_SOFT_RESET_CMD 0x08\r
-#define ATAPI_PACKET_CMD 0xA0\r
-#define PACKET_CMD 0xA0\r
-#define ATAPI_IDENTIFY_DEVICE_CMD 0xA1\r
-#define ATAPI_SERVICE_CMD 0xA2\r
-\r
-//\r
-// ATAPI Packet Command\r
-//\r
#pragma pack(1)\r
\r
-typedef struct {\r
- UINT8 opcode;\r
- UINT8 reserved_1;\r
- UINT8 reserved_2;\r
- UINT8 reserved_3;\r
- UINT8 reserved_4;\r
- UINT8 reserved_5;\r
- UINT8 reserved_6;\r
- UINT8 reserved_7;\r
- UINT8 reserved_8;\r
- UINT8 reserved_9;\r
- UINT8 reserved_10;\r
- UINT8 reserved_11;\r
-} TEST_UNIT_READY_CMD;\r
-\r
-typedef struct {\r
- UINT8 opcode;\r
- UINT8 reserved_1 : 4;\r
- UINT8 lun : 4;\r
- UINT8 page_code;\r
- UINT8 reserved_3;\r
- UINT8 allocation_length;\r
- UINT8 reserved_5;\r
- UINT8 reserved_6;\r
- UINT8 reserved_7;\r
- UINT8 reserved_8;\r
- UINT8 reserved_9;\r
- UINT8 reserved_10;\r
- UINT8 reserved_11;\r
-} INQUIRY_CMD;\r
-\r
-typedef struct {\r
- UINT8 opcode;\r
- UINT8 reserved_1 : 4;\r
- UINT8 lun : 4;\r
- UINT8 reserved_2;\r
- UINT8 reserved_3;\r
- UINT8 allocation_length;\r
- UINT8 reserved_5;\r
- UINT8 reserved_6;\r
- UINT8 reserved_7;\r
- UINT8 reserved_8;\r
- UINT8 reserved_9;\r
- UINT8 reserved_10;\r
- UINT8 reserved_11;\r
-} REQUEST_SENSE_CMD;\r
-\r
-typedef struct {\r
- UINT8 opcode;\r
- UINT8 reserved_1 : 4;\r
- UINT8 lun : 4;\r
- UINT8 page_code : 4;\r
- UINT8 page_control : 4;\r
- UINT8 reserved_3;\r
- UINT8 reserved_4;\r
- UINT8 reserved_5;\r
- UINT8 reserved_6;\r
- UINT8 parameter_list_length_hi;\r
- UINT8 parameter_list_length_lo;\r
- UINT8 reserved_9;\r
- UINT8 reserved_10;\r
- UINT8 reserved_11;\r
-} MODE_SENSE_CMD;\r
-\r
-typedef struct {\r
- UINT8 opcode;\r
- UINT8 reserved_1 : 5;\r
- UINT8 lun : 3;\r
- UINT8 Lba0;\r
- UINT8 Lba1;\r
- UINT8 Lba2;\r
- UINT8 Lba3;\r
- UINT8 reserved_6;\r
- UINT8 TranLen0;\r
- UINT8 TranLen1;\r
- UINT8 reserved_9;\r
- UINT8 reserved_10;\r
- UINT8 reserved_11;\r
-} READ10_CMD;\r
-\r
-typedef struct {\r
- UINT8 opcode;\r
- UINT8 reserved_1;\r
- UINT8 reserved_2;\r
- UINT8 reserved_3;\r
- UINT8 reserved_4;\r
- UINT8 reserved_5;\r
- UINT8 reserved_6;\r
- UINT8 allocation_length_hi;\r
- UINT8 allocation_length_lo;\r
- UINT8 reserved_9;\r
- UINT8 reserved_10;\r
- UINT8 reserved_11;\r
-} READ_FORMAT_CAP_CMD;\r
-\r
-typedef union {\r
- UINT16 Data16[6];\r
- TEST_UNIT_READY_CMD TestUnitReady;\r
- READ10_CMD Read10;\r
- REQUEST_SENSE_CMD RequestSence;\r
- INQUIRY_CMD Inquiry;\r
- MODE_SENSE_CMD ModeSense;\r
- READ_FORMAT_CAP_CMD ReadFormatCapacity;\r
-} ATAPI_PACKET_COMMAND;\r
-\r
typedef struct {\r
UINT32 RegionBaseAddr;\r
UINT16 ByteCount;\r
UINT16 EndOfTable;\r
} IDE_DMA_PRD;\r
\r
-#define MAX_DMA_EXT_COMMAND_SECTORS 0x10000\r
-#define MAX_DMA_COMMAND_SECTORS 0x100\r
-\r
#pragma pack()\r
\r
-//\r
-// Packet Command Code\r
-//\r
-#define TEST_UNIT_READY 0x00\r
-#define REZERO 0x01\r
-#define REQUEST_SENSE 0x03\r
-#define FORMAT_UNIT 0x04\r
-#define REASSIGN_BLOCKS 0x07\r
-#define INQUIRY 0x12\r
-#define START_STOP_UNIT 0x1B\r
-#define PREVENT_ALLOW_MEDIA_REMOVAL 0x1E\r
-#define READ_FORMAT_CAPACITY 0x23\r
-#define OLD_FORMAT_UNIT 0x24\r
-#define READ_CAPACITY 0x25\r
-#define READ_10 0x28\r
-#define WRITE_10 0x2A\r
-#define SEEK 0x2B\r
-#define SEND_DIAGNOSTICS 0x3D\r
-#define WRITE_VERIFY 0x2E\r
-#define VERIFY 0x2F\r
-#define READ_DEFECT_DATA 0x37\r
-#define WRITE_BUFFER 0x38\r
-#define READ_BUFFER 0x3C\r
-#define READ_LONG 0x3E\r
-#define WRITE_LONG 0x3F\r
-#define MODE_SELECT 0x55\r
-#define MODE_SENSE 0x5A\r
-#define READ_12 0xA8\r
-#define WRITE_12 0xAA\r
-#define MAX_ATAPI_BYTE_COUNT (0xfffe)\r
-\r
-//\r
-// Sense Key\r
-//\r
-#define REQUEST_SENSE_ERROR (0x70)\r
-#define SK_NO_SENSE (0x0)\r
-#define SK_RECOVERY_ERROR (0x1)\r
-#define SK_NOT_READY (0x2)\r
-#define SK_MEDIUM_ERROR (0x3)\r
-#define SK_HARDWARE_ERROR (0x4)\r
-#define SK_ILLEGAL_REQUEST (0x5)\r
-#define SK_UNIT_ATTENTION (0x6)\r
-#define SK_DATA_PROTECT (0x7)\r
-#define SK_BLANK_CHECK (0x8)\r
-#define SK_VENDOR_SPECIFIC (0x9)\r
-#define SK_RESERVED_A (0xA)\r
-#define SK_ABORT (0xB)\r
-#define SK_RESERVED_C (0xC)\r
-#define SK_OVERFLOW (0xD)\r
-#define SK_MISCOMPARE (0xE)\r
-#define SK_RESERVED_F (0xF)\r
-\r
-//\r
-// Additional Sense Codes\r
-//\r
-#define ASC_NOT_READY (0x04)\r
-#define ASC_MEDIA_ERR1 (0x10)\r
-#define ASC_MEDIA_ERR2 (0x11)\r
-#define ASC_MEDIA_ERR3 (0x14)\r
-#define ASC_MEDIA_ERR4 (0x30)\r
-#define ASC_MEDIA_UPSIDE_DOWN (0x06)\r
-#define ASC_INVALID_CMD (0x20)\r
-#define ASC_LBA_OUT_OF_RANGE (0x21)\r
-#define ASC_INVALID_FIELD (0x24)\r
-#define ASC_WRITE_PROTECTED (0x27)\r
-#define ASC_MEDIA_CHANGE (0x28)\r
-#define ASC_RESET (0x29) /* Power On Reset or Bus Reset occurred */\r
-#define ASC_ILLEGAL_FIELD (0x26)\r
-#define ASC_NO_MEDIA (0x3A)\r
-#define ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64)\r
-\r
-//\r
-// Additional Sense Code Qualifier\r
-//\r
-#define ASCQ_IN_PROGRESS (0x01)\r
-\r
#define SETFEATURE TRUE\r
#define CLEARFEATURE FALSE\r
\r
-//\r
-// ATAPI Data structure\r
-//\r
-#pragma pack(1)\r
-\r
-typedef struct {\r
- UINT8 peripheral_type;\r
- UINT8 RMB;\r
- UINT8 version;\r
- UINT8 response_data_format;\r
- UINT8 addnl_length;\r
- UINT8 reserved_5;\r
- UINT8 reserved_6;\r
- UINT8 reserved_7;\r
- UINT8 vendor_info[8];\r
- UINT8 product_id[12];\r
- UINT8 eeprom_product_code[4];\r
- UINT8 firmware_rev_level[4];\r
- UINT8 firmware_sub_rev_level[1];\r
- UINT8 reserved_37;\r
- UINT8 reserved_38;\r
- UINT8 reserved_39;\r
- UINT8 max_capacity_hi;\r
- UINT8 max_capacity_mid;\r
- UINT8 max_capacity_lo;\r
- UINT8 reserved_43_95[95 - 43 + 1];\r
-} INQUIRY_DATA;\r
-\r
-typedef struct {\r
- UINT8 peripheral_type;\r
- UINT8 RMB;\r
- UINT8 version;\r
- UINT8 response_data_format;\r
- UINT8 addnl_length;\r
- UINT8 reserved_5;\r
- UINT8 reserved_6;\r
- UINT8 reserved_7;\r
- UINT8 vendor_info[8];\r
- UINT8 product_id[16];\r
- UINT8 product_revision_level[4];\r
- UINT8 vendor_specific[20];\r
- UINT8 reserved_56_95[40];\r
-} CDROM_INQUIRY_DATA;\r
-\r
-typedef struct {\r
- UINT8 error_code : 7;\r
- UINT8 valid : 1;\r
- UINT8 reserved_1;\r
- UINT8 sense_key : 4;\r
- UINT8 reserved_21 : 1;\r
- UINT8 ILI : 1;\r
- UINT8 reserved_22 : 2;\r
- UINT8 vendor_specific_3;\r
- UINT8 vendor_specific_4;\r
- UINT8 vendor_specific_5;\r
- UINT8 vendor_specific_6;\r
- UINT8 addnl_sense_length; // n - 7\r
- UINT8 vendor_specific_8;\r
- UINT8 vendor_specific_9;\r
- UINT8 vendor_specific_10;\r
- UINT8 vendor_specific_11;\r
- UINT8 addnl_sense_code; // mandatory\r
- UINT8 addnl_sense_code_qualifier; // mandatory\r
- UINT8 field_replaceable_unit_code; // optional\r
- UINT8 reserved_15;\r
- UINT8 reserved_16;\r
- UINT8 reserved_17;\r
- //\r
- // Followed by additional sense bytes : FIXME\r
- //\r
-} REQUEST_SENSE_DATA;\r
-\r
-typedef struct {\r
- UINT8 LastLba3;\r
- UINT8 LastLba2;\r
- UINT8 LastLba1;\r
- UINT8 LastLba0;\r
- UINT8 BlockSize3;\r
- UINT8 BlockSize2;\r
- UINT8 BlockSize1;\r
- UINT8 BlockSize0;\r
-} READ_CAPACITY_DATA;\r
-\r
-typedef struct {\r
- UINT8 reserved_0;\r
- UINT8 reserved_1;\r
- UINT8 reserved_2;\r
- UINT8 Capacity_Length;\r
- UINT8 LastLba3;\r
- UINT8 LastLba2;\r
- UINT8 LastLba1;\r
- UINT8 LastLba0;\r
- UINT8 DesCode : 2;\r
- UINT8 reserved_9 : 6;\r
- UINT8 BlockSize2;\r
- UINT8 BlockSize1;\r
- UINT8 BlockSize0;\r
-} READ_FORMAT_CAPACITY_DATA;\r
-\r
-#pragma pack()\r
-\r
//\r
// PIO mode definition\r
//\r
//\r
// Slave IDE Timing Register Enable\r
//\r
-#define SITRE bit14\r
+#define SITRE BIT14\r
\r
//\r
// DMA Timing Enable Only Select 1\r
//\r
-#define DTE1 bit7\r
+#define DTE1 BIT7\r
\r
//\r
// Pre-fetch and Posting Enable Select 1\r
//\r
-#define PPE1 bit6\r
+#define PPE1 BIT6\r
\r
//\r
// IORDY Sample Point Enable Select 1\r
//\r
-#define IE1 bit5\r
+#define IE1 BIT5\r
\r
//\r
// Fast Timing Bank Drive Select 1\r
//\r
-#define TIME1 bit4\r
+#define TIME1 BIT4\r
\r
//\r
// DMA Timing Enable Only Select 0\r
//\r
-#define DTE0 bit3\r
+#define DTE0 BIT3\r
\r
//\r
// Pre-fetch and Posting Enable Select 0\r
//\r
-#define PPE0 bit2\r
+#define PPE0 BIT2\r
\r
//\r
// IOREY Sample Point Enable Select 0\r
//\r
-#define IE0 bit1\r
+#define IE0 BIT1\r
\r
//\r
// Fast Timing Bank Drive Select 0\r
//\r
-#define TIME0 bit0\r
+#define TIME0 BIT0\r
\r
#endif\r
projects / mirror_edk2.git / blobdiff