Add PciBus & IdeBus

[mirror_edk2.git] / IntelFrameworkModulePkg / Bus / Pci / PciBus / Dxe / PciCommand.c

diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBus/Dxe/PciCommand.c b/IntelFrameworkModulePkg/Bus/Pci/PciBus/Dxe/PciCommand.c
new file mode 100644 (file)
index 0000000..dd4b650
--- /dev/null
+++ b/IntelFrameworkModulePkg/Bus/Pci/PciBus/Dxe/PciCommand.c
@@ -0,0 +1,207 @@
+/*++\r
+\r
+Copyright (c) 2006 - 2007, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+Module Name:\r
+\r
+  PciCommand.c\r
+\r
+Abstract:\r
+\r
+  PCI Bus Driver\r
+\r
+Revision History\r
+\r
+--*/\r
+\r
+#include "pcibus.h"\r
+\r
+EFI_STATUS\r
+PciOperateRegister (\r
+  IN  PCI_IO_DEVICE *PciIoDevice,\r
+  IN  UINT16        Command,\r
+  IN  UINT8         Offset,\r
+  IN  UINT8         Operation,\r
+  OUT UINT16        *PtrCommand\r
+  )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+Arguments:\r
+\r
+Returns:\r
+\r
+  None\r
+\r
+--*/\r
+// TODO:    PciIoDevice - add argument and description to function comment\r
+// TODO:    Command - add argument and description to function comment\r
+// TODO:    Offset - add argument and description to function comment\r
+// TODO:    Operation - add argument and description to function comment\r
+// TODO:    PtrCommand - add argument and description to function comment\r
+{\r
+  UINT16              OldCommand;\r
+  EFI_STATUS          Status;\r
+  EFI_PCI_IO_PROTOCOL *PciIo;\r
+\r
+  OldCommand  = 0;\r
+  PciIo       = &PciIoDevice->PciIo;\r
+\r
+  if (Operation != EFI_SET_REGISTER) {\r
+    Status = PciIoRead (\r
+                         PciIo,\r
+                         EfiPciIoWidthUint16,\r
+                         Offset,\r
+                         1,\r
+                         &OldCommand\r
+                        );\r
+\r
+    if (Operation == EFI_GET_REGISTER) {\r
+      *PtrCommand = OldCommand;\r
+      return Status;\r
+    }\r
+  }\r
+\r
+  if (Operation == EFI_ENABLE_REGISTER) {\r
+    OldCommand = (UINT16) (OldCommand | Command);\r
+  } else if (Operation == EFI_DISABLE_REGISTER) {\r
+    OldCommand = (UINT16) (OldCommand & ~(Command));\r
+  } else {\r
+    OldCommand = Command;\r
+  }\r
+\r
+  return PciIoWrite (\r
+                      PciIo,\r
+                      EfiPciIoWidthUint16,\r
+                      Offset,\r
+                      1,\r
+                      &OldCommand\r
+                    );\r
+}\r
+\r
+BOOLEAN\r
+PciCapabilitySupport (\r
+  IN PCI_IO_DEVICE  *PciIoDevice\r
+  )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+Arguments:\r
+\r
+Returns:\r
+\r
+  None\r
+\r
+--*/\r
+// TODO:    PciIoDevice - add argument and description to function comment\r
+{\r
+\r
+  if (PciIoDevice->Pci.Hdr.Status & EFI_PCI_STATUS_CAPABILITY) {\r
+    return TRUE;\r
+  }\r
+\r
+  return FALSE;\r
+}\r
+\r
+EFI_STATUS\r
+LocateCapabilityRegBlock (\r
+  IN PCI_IO_DEVICE  *PciIoDevice,\r
+  IN UINT8          CapId,\r
+  IN OUT UINT8      *Offset,\r
+  OUT UINT8         *NextRegBlock OPTIONAL\r
+  )\r
+/*++\r
+\r
+Routine Description:\r
+  Locate cap reg.\r
+\r
+Arguments:\r
+  PciIoDevice         - A pointer to the PCI_IO_DEVICE.\r
+  CapId               - The cap ID.\r
+  Offset              - A pointer to the offset.\r
+  NextRegBlock        - A pointer to the next block.\r
+\r
+Returns:\r
+\r
+  None\r
+\r
+--*/\r
+// TODO:    EFI_UNSUPPORTED - add return value to function comment\r
+// TODO:    EFI_SUCCESS - add return value to function comment\r
+// TODO:    EFI_NOT_FOUND - add return value to function comment\r
+{\r
+  UINT8   CapabilityPtr;\r
+  UINT16  CapabilityEntry;\r
+  UINT8   CapabilityID;\r
+\r
+  //\r
+  // To check the cpability of this device supports\r
+  //\r
+  if (!PciCapabilitySupport (PciIoDevice)) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  if (*Offset != 0) {\r
+    CapabilityPtr = *Offset;\r
+  } else {\r
+\r
+    CapabilityPtr = 0;\r
+    if (IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {\r
+\r
+      PciIoRead (\r
+                  &PciIoDevice->PciIo,\r
+                  EfiPciIoWidthUint8,\r
+                  EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR,\r
+                  1,\r
+                  &CapabilityPtr\r
+                );\r
+    } else {\r
+\r
+      PciIoRead (\r
+                  &PciIoDevice->PciIo,\r
+                  EfiPciIoWidthUint8,\r
+                  EFI_PCI_CAPABILITY_PTR,\r
+                  1,\r
+                  &CapabilityPtr\r
+                );\r
+    }\r
+  }\r
+\r
+  while (CapabilityPtr > 0x3F) {\r
+    //\r
+    // Mask it to DWORD alignment per PCI spec\r
+    //\r
+    CapabilityPtr &= 0xFC;\r
+    PciIoRead (\r
+                &PciIoDevice->PciIo,\r
+                EfiPciIoWidthUint16,\r
+                CapabilityPtr,\r
+                1,\r
+                &CapabilityEntry\r
+              );\r
+\r
+    CapabilityID = (UINT8) CapabilityEntry;\r
+\r
+    if (CapabilityID == CapId) {\r
+      *Offset = CapabilityPtr;\r
+      if (NextRegBlock != NULL) {\r
+        *NextRegBlock = (UINT8) (CapabilityEntry >> 8);\r
+      }\r
+\r
+      return EFI_SUCCESS;\r
+    }\r
+\r
+    CapabilityPtr = (UINT8) (CapabilityEntry >> 8);\r
+  }\r
+\r
+  return EFI_NOT_FOUND;\r
+}\r