+++ /dev/null
-/*++\r
-\r
-Copyright (c) 2006 - 2007, Intel Corporation\r
-All rights reserved. This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution. The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
-\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-Module Name:\r
-\r
- PciLib.c\r
-\r
-Abstract:\r
-\r
- PCI Bus Driver Lib file\r
- It abstracts some functions that can be different\r
- between light PCI bus driver and full PCI bus driver\r
-\r
-Revision History\r
-\r
---*/\r
-\r
-#include "pcibus.h"\r
-\r
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_PCI_HOTPLUG_REQUEST_PROTOCOL gPciHotPlugRequest = {\r
- PciHotPlugRequestNotify\r
-};\r
-\r
-\r
-VOID\r
-InstallHotPlugRequestProtocol (\r
- IN EFI_STATUS *Status\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
- Status - A pointer to the status.\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-{\r
- EFI_HANDLE Handle;\r
-\r
- if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
- return;\r
- }\r
-\r
- Handle = NULL;\r
- *Status = gBS->InstallProtocolInterface (\r
- &Handle,\r
- &gEfiPciHotPlugRequestProtocolGuid,\r
- EFI_NATIVE_INTERFACE,\r
- &gPciHotPlugRequest\r
- );\r
-}\r
-\r
-VOID\r
-InstallPciHotplugGuid (\r
- IN PCI_IO_DEVICE *PciIoDevice\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
-\r
- PciIoDevice - A pointer to the PCI_IO_DEVICE.\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-{\r
- EFI_STATUS Status;\r
-\r
- if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
- return;\r
- }\r
-\r
- if (IS_CARDBUS_BRIDGE (&PciIoDevice->Parent->Pci)) {\r
-\r
- Status = gBS->InstallProtocolInterface (\r
- &PciIoDevice->Handle,\r
- &gEfiPciHotplugDeviceGuid,\r
- EFI_NATIVE_INTERFACE,\r
- NULL\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
- }\r
-}\r
-\r
-VOID\r
-UninstallPciHotplugGuid (\r
- IN PCI_IO_DEVICE *PciIoDevice\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
-\r
- PciIoDevice - A pointer to the PCI_IO_DEVICE.\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-{\r
- EFI_STATUS Status;\r
-\r
- if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
- return;\r
- }\r
-\r
- Status = gBS->OpenProtocol (\r
- PciIoDevice->Handle,\r
- &gEfiPciHotplugDeviceGuid,\r
- NULL,\r
- NULL,\r
- NULL,\r
- EFI_OPEN_PROTOCOL_TEST_PROTOCOL\r
- );\r
-\r
- if (Status == EFI_SUCCESS) {\r
- //\r
- // This may triger CardBus driver to stop for\r
- // Pccard devices opened the GUID via BY_DRIVER\r
- //\r
- Status = gBS->UninstallProtocolInterface (\r
- PciIoDevice->Handle,\r
- &gEfiPciHotplugDeviceGuid,\r
- NULL\r
- );\r
- }\r
-}\r
-\r
-VOID\r
-GetBackPcCardBar (\r
- IN PCI_IO_DEVICE *PciIoDevice\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
-\r
-Arguments:\r
-\r
- PciIoDevice - A pointer to the PCI_IO_DEVICE.\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-{\r
- UINT32 Address;\r
-\r
- if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
- return;\r
- }\r
-\r
- //\r
- // Read PciBar information from the bar register\r
- //\r
- if (!gFullEnumeration) {\r
-\r
- Address = 0;\r
- PciIoRead (\r
- &(PciIoDevice->PciIo),\r
- EfiPciIoWidthUint32,\r
- 0x1c,\r
- 1,\r
- &Address\r
- );\r
-\r
- (PciIoDevice->PciBar)[P2C_MEM_1].BaseAddress = (UINT64) (Address);\r
- (PciIoDevice->PciBar)[P2C_MEM_1].Length = 0x2000000;\r
- (PciIoDevice->PciBar)[P2C_MEM_1].BarType = PciBarTypeMem32;\r
-\r
- Address = 0;\r
- PciIoRead (\r
- &(PciIoDevice->PciIo),\r
- EfiPciIoWidthUint32,\r
- 0x20,\r
- 1,\r
- &Address\r
- );\r
- (PciIoDevice->PciBar)[P2C_MEM_2].BaseAddress = (UINT64) (Address);\r
- (PciIoDevice->PciBar)[P2C_MEM_2].Length = 0x2000000;\r
- (PciIoDevice->PciBar)[P2C_MEM_2].BarType = PciBarTypePMem32;\r
-\r
- Address = 0;\r
- PciIoRead (\r
- &(PciIoDevice->PciIo),\r
- EfiPciIoWidthUint32,\r
- 0x2c,\r
- 1,\r
- &Address\r
- );\r
- (PciIoDevice->PciBar)[P2C_IO_1].BaseAddress = (UINT64) (Address);\r
- (PciIoDevice->PciBar)[P2C_IO_1].Length = 0x100;\r
- (PciIoDevice->PciBar)[P2C_IO_1].BarType = PciBarTypeIo16;\r
-\r
- Address = 0;\r
- PciIoRead (\r
- &(PciIoDevice->PciIo),\r
- EfiPciIoWidthUint32,\r
- 0x34,\r
- 1,\r
- &Address\r
- );\r
- (PciIoDevice->PciBar)[P2C_IO_2].BaseAddress = (UINT64) (Address);\r
- (PciIoDevice->PciBar)[P2C_IO_2].Length = 0x100;\r
- (PciIoDevice->PciBar)[P2C_IO_2].BarType = PciBarTypeIo16;\r
-\r
- }\r
-\r
- if (gPciHotPlugInit != NULL) {\r
- GetResourcePaddingForHpb (PciIoDevice);\r
- }\r
-}\r
-\r
-EFI_STATUS\r
-RemoveRejectedPciDevices (\r
- EFI_HANDLE RootBridgeHandle,\r
- IN PCI_IO_DEVICE *Bridge\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
-\r
-Arguments:\r
-\r
- RootBridgeHandle - An efi handle.\r
- Bridge - An pointer to the PCI_IO_DEVICE.\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
-{\r
- PCI_IO_DEVICE *Temp;\r
- LIST_ENTRY *CurrentLink;\r
- LIST_ENTRY *LastLink;\r
-\r
- if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
- return EFI_SUCCESS;\r
- }\r
-\r
- CurrentLink = Bridge->ChildList.ForwardLink;\r
-\r
- while (CurrentLink && CurrentLink != &Bridge->ChildList) {\r
-\r
- Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);\r
-\r
- if (IS_PCI_BRIDGE (&Temp->Pci)) {\r
- //\r
- // Remove rejected devices recusively\r
- //\r
- RemoveRejectedPciDevices (RootBridgeHandle, Temp);\r
- } else {\r
- //\r
- // Skip rejection for all PPBs, while detect rejection for others\r
- //\r
- if (IsPciDeviceRejected (Temp)) {\r
-\r
- //\r
- // For P2C, remove all devices on it\r
- //\r
-\r
- if (!IsListEmpty (&Temp->ChildList)) {\r
- RemoveAllPciDeviceOnBridge (RootBridgeHandle, Temp);\r
- }\r
-\r
- //\r
- // Finally remove itself\r
- //\r
-\r
- LastLink = CurrentLink->BackLink;\r
- RemoveEntryList (CurrentLink);\r
- FreePciDevice (Temp);\r
-\r
- CurrentLink = LastLink;\r
- }\r
- }\r
-\r
- CurrentLink = CurrentLink->ForwardLink;\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-EFI_STATUS\r
-PciHostBridgeResourceAllocator (\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
- )\r
-{\r
- if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
- return PciHostBridgeResourceAllocator_WithHotPlugDeviceSupport (\r
- PciResAlloc\r
- );\r
- } else {\r
- return PciHostBridgeResourceAllocator_WithoutHotPlugDeviceSupport (\r
- PciResAlloc\r
- );\r
- }\r
-}\r
-\r
-\r
-EFI_STATUS\r
-PciHostBridgeResourceAllocator_WithoutHotPlugDeviceSupport (\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-// TODO: PciResAlloc - add argument and description to function comment\r
-// TODO: EFI_NOT_FOUND - add return value to function comment\r
-// TODO: EFI_OUT_OF_RESOURCES - add return value to function comment\r
-// TODO: EFI_NOT_FOUND - add return value to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
-{\r
- PCI_IO_DEVICE *RootBridgeDev;\r
- EFI_HANDLE RootBridgeHandle;\r
- VOID *AcpiConfig;\r
- EFI_STATUS Status;\r
- UINT64 IoBase;\r
- UINT64 Mem32Base;\r
- UINT64 PMem32Base;\r
- UINT64 Mem64Base;\r
- UINT64 PMem64Base;\r
- UINT64 MaxOptionRomSize;\r
- PCI_RESOURCE_NODE *IoBridge;\r
- PCI_RESOURCE_NODE *Mem32Bridge;\r
- PCI_RESOURCE_NODE *PMem32Bridge;\r
- PCI_RESOURCE_NODE *Mem64Bridge;\r
- PCI_RESOURCE_NODE *PMem64Bridge;\r
- PCI_RESOURCE_NODE IoPool;\r
- PCI_RESOURCE_NODE Mem32Pool;\r
- PCI_RESOURCE_NODE PMem32Pool;\r
- PCI_RESOURCE_NODE Mem64Pool;\r
- PCI_RESOURCE_NODE PMem64Pool;\r
- EFI_DEVICE_HANDLE_EXTENDED_DATA_PAYLOAD ExtendedData;\r
-\r
- //\r
- // Initialize resource pool\r
- //\r
-\r
- InitializeResourcePool (&IoPool, PciBarTypeIo16);\r
- InitializeResourcePool (&Mem32Pool, PciBarTypeMem32);\r
- InitializeResourcePool (&PMem32Pool, PciBarTypePMem32);\r
- InitializeResourcePool (&Mem64Pool, PciBarTypeMem64);\r
- InitializeResourcePool (&PMem64Pool, PciBarTypePMem64);\r
-\r
- RootBridgeDev = NULL;\r
- RootBridgeHandle = 0;\r
-\r
- while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
- //\r
- // Get RootBridg Device by handle\r
- //\r
- RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);\r
-\r
- if (RootBridgeDev == NULL) {\r
- return EFI_NOT_FOUND;\r
- }\r
-\r
- //\r
- // Get host bridge handle for status report\r
- //\r
- ExtendedData.Handle = RootBridgeDev->PciRootBridgeIo->ParentHandle;\r
-\r
- //\r
- // Create the entire system resource map from the information collected by\r
- // enumerator. Several resource tree was created\r
- //\r
-\r
- IoBridge = CreateResourceNode (\r
- RootBridgeDev,\r
- 0,\r
- 0xFFF,\r
- 0,\r
- PciBarTypeIo16,\r
- PciResUsageTypical\r
- );\r
-\r
- Mem32Bridge = CreateResourceNode (\r
- RootBridgeDev,\r
- 0,\r
- 0xFFFFF,\r
- 0,\r
- PciBarTypeMem32,\r
- PciResUsageTypical\r
- );\r
-\r
- PMem32Bridge = CreateResourceNode (\r
- RootBridgeDev,\r
- 0,\r
- 0xFFFFF,\r
- 0,\r
- PciBarTypePMem32,\r
- PciResUsageTypical\r
- );\r
-\r
- Mem64Bridge = CreateResourceNode (\r
- RootBridgeDev,\r
- 0,\r
- 0xFFFFF,\r
- 0,\r
- PciBarTypeMem64,\r
- PciResUsageTypical\r
- );\r
-\r
- PMem64Bridge = CreateResourceNode (\r
- RootBridgeDev,\r
- 0,\r
- 0xFFFFF,\r
- 0,\r
- PciBarTypePMem64,\r
- PciResUsageTypical\r
- );\r
-\r
- //\r
- // Create resourcemap by going through all the devices subject to this root bridge\r
- //\r
- Status = CreateResourceMap (\r
- RootBridgeDev,\r
- IoBridge,\r
- Mem32Bridge,\r
- PMem32Bridge,\r
- Mem64Bridge,\r
- PMem64Bridge\r
- );\r
-\r
- //\r
- // Get the max ROM size that the root bridge can process\r
- //\r
- RootBridgeDev->RomSize = Mem32Bridge->Length;\r
-\r
- //\r
- // Get Max Option Rom size for current root bridge\r
- //\r
- MaxOptionRomSize = GetMaxOptionRomSize (RootBridgeDev);\r
-\r
- //\r
- // Enlarger the mem32 resource to accomdate the option rom\r
- // if the mem32 resource is not enough to hold the rom\r
- //\r
- if (MaxOptionRomSize > Mem32Bridge->Length) {\r
-\r
- Mem32Bridge->Length = MaxOptionRomSize;\r
- RootBridgeDev->RomSize = MaxOptionRomSize;\r
-\r
- //\r
- // Alignment should be adjusted as well\r
- //\r
- if (Mem32Bridge->Alignment < MaxOptionRomSize - 1) {\r
- Mem32Bridge->Alignment = MaxOptionRomSize - 1;\r
- }\r
- }\r
-\r
- //\r
- // Based on the all the resource tree, contruct ACPI resource node to\r
- // submit the resource aperture to pci host bridge protocol\r
- //\r
- Status = ConstructAcpiResourceRequestor (\r
- RootBridgeDev,\r
- IoBridge,\r
- Mem32Bridge,\r
- PMem32Bridge,\r
- Mem64Bridge,\r
- PMem64Bridge,\r
- &AcpiConfig\r
- );\r
-\r
- //\r
- // Insert these resource nodes into the database\r
- //\r
- InsertResourceNode (&IoPool, IoBridge);\r
- InsertResourceNode (&Mem32Pool, Mem32Bridge);\r
- InsertResourceNode (&PMem32Pool, PMem32Bridge);\r
- InsertResourceNode (&Mem64Pool, Mem64Bridge);\r
- InsertResourceNode (&PMem64Pool, PMem64Bridge);\r
-\r
- if (Status == EFI_SUCCESS) {\r
- //\r
- // Submit the resource requirement\r
- //\r
- Status = PciResAlloc->SubmitResources (\r
- PciResAlloc,\r
- RootBridgeDev->Handle,\r
- AcpiConfig\r
- );\r
- }\r
- //\r
- // Free acpi resource node\r
- //\r
- if (AcpiConfig != NULL) {\r
- FreePool (AcpiConfig);\r
- }\r
-\r
- if (EFI_ERROR (Status)) {\r
- //\r
- // Destroy all the resource tree\r
- //\r
- DestroyResourceTree (&IoPool);\r
- DestroyResourceTree (&Mem32Pool);\r
- DestroyResourceTree (&PMem32Pool);\r
- DestroyResourceTree (&Mem64Pool);\r
- DestroyResourceTree (&PMem64Pool);\r
- return Status;\r
- }\r
- }\r
- //\r
- // End while\r
- //\r
-\r
- //\r
- // Notify pci bus driver starts to program the resource\r
- //\r
- Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeAllocateResources);\r
-\r
- if (EFI_ERROR (Status)) {\r
- //\r
- // Allocation failed, then return\r
- //\r
- return EFI_OUT_OF_RESOURCES;\r
- }\r
- //\r
- // Raise the EFI_IOB_PCI_RES_ALLOC status code\r
- //\r
- REPORT_STATUS_CODE_WITH_EXTENDED_DATA (\r
- EFI_PROGRESS_CODE,\r
- EFI_IO_BUS_PCI | EFI_IOB_PCI_PC_RES_ALLOC,\r
- (VOID *) &ExtendedData,\r
- sizeof (ExtendedData)\r
- );\r
-\r
- //\r
- // Notify pci bus driver starts to program the resource\r
- //\r
- NotifyPhase (PciResAlloc, EfiPciHostBridgeSetResources);\r
-\r
- RootBridgeDev = NULL;\r
-\r
- RootBridgeHandle = 0;\r
-\r
- while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
- //\r
- // Get RootBridg Device by handle\r
- //\r
- RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);\r
-\r
- if (RootBridgeDev == NULL) {\r
- return EFI_NOT_FOUND;\r
- }\r
-\r
- //\r
- // Get acpi resource node for all the resource types\r
- //\r
- AcpiConfig = NULL;\r
- Status = PciResAlloc->GetProposedResources (\r
- PciResAlloc,\r
- RootBridgeDev->Handle,\r
- &AcpiConfig\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- //\r
- // Get the resource base by interpreting acpi resource node\r
- //\r
- //\r
- GetResourceBase (\r
- AcpiConfig,\r
- &IoBase,\r
- &Mem32Base,\r
- &PMem32Base,\r
- &Mem64Base,\r
- &PMem64Base\r
- );\r
-\r
- //\r
- // Process option rom for this root bridge\r
- //\r
- Status = ProcessOptionRom (RootBridgeDev, Mem32Base, RootBridgeDev->RomSize);\r
-\r
- //\r
- // Create the entire system resource map from the information collected by\r
- // enumerator. Several resource tree was created\r
- //\r
- Status = GetResourceMap (\r
- RootBridgeDev,\r
- &IoBridge,\r
- &Mem32Bridge,\r
- &PMem32Bridge,\r
- &Mem64Bridge,\r
- &PMem64Bridge,\r
- &IoPool,\r
- &Mem32Pool,\r
- &PMem32Pool,\r
- &Mem64Pool,\r
- &PMem64Pool\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- //\r
- // Program IO resources\r
- //\r
- ProgramResource (\r
- IoBase,\r
- IoBridge\r
- );\r
-\r
- //\r
- // Program Mem32 resources\r
- //\r
- ProgramResource (\r
- Mem32Base,\r
- Mem32Bridge\r
- );\r
-\r
- //\r
- // Program PMem32 resources\r
- //\r
- ProgramResource (\r
- PMem32Base,\r
- PMem32Bridge\r
- );\r
-\r
- //\r
- // Program Mem64 resources\r
- //\r
- ProgramResource (\r
- Mem64Base,\r
- Mem64Bridge\r
- );\r
-\r
- //\r
- // Program PMem64 resources\r
- //\r
- ProgramResource (\r
- PMem64Base,\r
- PMem64Bridge\r
- );\r
-\r
- if (AcpiConfig != NULL) {\r
- FreePool (AcpiConfig);\r
- }\r
- }\r
-\r
- //\r
- // Destroy all the resource tree\r
- //\r
- DestroyResourceTree (&IoPool);\r
- DestroyResourceTree (&Mem32Pool);\r
- DestroyResourceTree (&PMem32Pool);\r
- DestroyResourceTree (&Mem64Pool);\r
- DestroyResourceTree (&PMem64Pool);\r
-\r
- //\r
- // Notify the resource allocation phase is to end\r
- //\r
- NotifyPhase (PciResAlloc, EfiPciHostBridgeEndResourceAllocation);\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-\r
-EFI_STATUS\r
-PciHostBridgeResourceAllocator_WithHotPlugDeviceSupport (\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Host brige resource allocator.\r
-\r
-Arguments:\r
-\r
- PciResAlloc - A pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
-\r
-Returns:\r
-\r
- EFI Status.\r
-\r
---*/\r
-// TODO: EFI_NOT_FOUND - add return value to function comment\r
-// TODO: EFI_NOT_FOUND - add return value to function comment\r
-// TODO: EFI_NOT_FOUND - add return value to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
-{\r
- PCI_IO_DEVICE *RootBridgeDev;\r
- EFI_HANDLE RootBridgeHandle;\r
- VOID *AcpiConfig;\r
- EFI_STATUS Status;\r
- UINT64 IoBase;\r
- UINT64 Mem32Base;\r
- UINT64 PMem32Base;\r
- UINT64 Mem64Base;\r
- UINT64 PMem64Base;\r
- UINT64 IoResStatus;\r
- UINT64 Mem32ResStatus;\r
- UINT64 PMem32ResStatus;\r
- UINT64 Mem64ResStatus;\r
- UINT64 PMem64ResStatus;\r
- UINT64 MaxOptionRomSize;\r
- PCI_RESOURCE_NODE *IoBridge;\r
- PCI_RESOURCE_NODE *Mem32Bridge;\r
- PCI_RESOURCE_NODE *PMem32Bridge;\r
- PCI_RESOURCE_NODE *Mem64Bridge;\r
- PCI_RESOURCE_NODE *PMem64Bridge;\r
- PCI_RESOURCE_NODE IoPool;\r
- PCI_RESOURCE_NODE Mem32Pool;\r
- PCI_RESOURCE_NODE PMem32Pool;\r
- PCI_RESOURCE_NODE Mem64Pool;\r
- PCI_RESOURCE_NODE PMem64Pool;\r
- BOOLEAN ReAllocate;\r
- EFI_DEVICE_HANDLE_EXTENDED_DATA_PAYLOAD HandleExtendedData;\r
- EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD AllocFailExtendedData;\r
-\r
- //\r
- // Reallocate flag\r
- //\r
- ReAllocate = FALSE;\r
-\r
- //\r
- // It will try several times if the resource allocation fails\r
- //\r
- while (TRUE) {\r
-\r
- //\r
- // Initialize resource pool\r
- //\r
- InitializeResourcePool (&IoPool, PciBarTypeIo16);\r
- InitializeResourcePool (&Mem32Pool, PciBarTypeMem32);\r
- InitializeResourcePool (&PMem32Pool, PciBarTypePMem32);\r
- InitializeResourcePool (&Mem64Pool, PciBarTypeMem64);\r
- InitializeResourcePool (&PMem64Pool, PciBarTypePMem64);\r
-\r
- RootBridgeDev = NULL;\r
- RootBridgeHandle = 0;\r
-\r
- while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
-\r
- //\r
- // Get RootBridg Device by handle\r
- //\r
- RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);\r
-\r
- if (RootBridgeDev == NULL) {\r
- return EFI_NOT_FOUND;\r
- }\r
-\r
- //\r
- // Create the entire system resource map from the information collected by\r
- // enumerator. Several resource tree was created\r
- //\r
-\r
- IoBridge = CreateResourceNode (\r
- RootBridgeDev,\r
- 0,\r
- 0xFFF,\r
- 0,\r
- PciBarTypeIo16,\r
- PciResUsageTypical\r
- );\r
-\r
- Mem32Bridge = CreateResourceNode (\r
- RootBridgeDev,\r
- 0,\r
- 0xFFFFF,\r
- 0,\r
- PciBarTypeMem32,\r
- PciResUsageTypical\r
- );\r
-\r
- PMem32Bridge = CreateResourceNode (\r
- RootBridgeDev,\r
- 0,\r
- 0xFFFFF,\r
- 0,\r
- PciBarTypePMem32,\r
- PciResUsageTypical\r
- );\r
-\r
- Mem64Bridge = CreateResourceNode (\r
- RootBridgeDev,\r
- 0,\r
- 0xFFFFF,\r
- 0,\r
- PciBarTypeMem64,\r
- PciResUsageTypical\r
- );\r
-\r
- PMem64Bridge = CreateResourceNode (\r
- RootBridgeDev,\r
- 0,\r
- 0xFFFFF,\r
- 0,\r
- PciBarTypePMem64,\r
- PciResUsageTypical\r
- );\r
-\r
- //\r
- // Create resourcemap by going through all the devices subject to this root bridge\r
- //\r
- Status = CreateResourceMap (\r
- RootBridgeDev,\r
- IoBridge,\r
- Mem32Bridge,\r
- PMem32Bridge,\r
- Mem64Bridge,\r
- PMem64Bridge\r
- );\r
-\r
- //\r
- // Get the max ROM size that the root bridge can process\r
- //\r
- RootBridgeDev->RomSize = Mem32Bridge->Length;\r
-\r
- //\r
- // Skip to enlarge the resource request during realloction\r
- //\r
- if (!ReAllocate) {\r
- //\r
- // Get Max Option Rom size for current root bridge\r
- //\r
- MaxOptionRomSize = GetMaxOptionRomSize (RootBridgeDev);\r
-\r
- //\r
- // Enlarger the mem32 resource to accomdate the option rom\r
- // if the mem32 resource is not enough to hold the rom\r
- //\r
- if (MaxOptionRomSize > Mem32Bridge->Length) {\r
-\r
- Mem32Bridge->Length = MaxOptionRomSize;\r
- RootBridgeDev->RomSize = MaxOptionRomSize;\r
-\r
- //\r
- // Alignment should be adjusted as well\r
- //\r
- if (Mem32Bridge->Alignment < MaxOptionRomSize - 1) {\r
- Mem32Bridge->Alignment = MaxOptionRomSize - 1;\r
- }\r
- }\r
- }\r
-\r
- //\r
- // Based on the all the resource tree, contruct ACPI resource node to\r
- // submit the resource aperture to pci host bridge protocol\r
- //\r
- Status = ConstructAcpiResourceRequestor (\r
- RootBridgeDev,\r
- IoBridge,\r
- Mem32Bridge,\r
- PMem32Bridge,\r
- Mem64Bridge,\r
- PMem64Bridge,\r
- &AcpiConfig\r
- );\r
-\r
- //\r
- // Insert these resource nodes into the database\r
- //\r
- InsertResourceNode (&IoPool, IoBridge);\r
- InsertResourceNode (&Mem32Pool, Mem32Bridge);\r
- InsertResourceNode (&PMem32Pool, PMem32Bridge);\r
- InsertResourceNode (&Mem64Pool, Mem64Bridge);\r
- InsertResourceNode (&PMem64Pool, PMem64Bridge);\r
-\r
- if (Status == EFI_SUCCESS) {\r
- //\r
- // Submit the resource requirement\r
- //\r
- Status = PciResAlloc->SubmitResources (\r
- PciResAlloc,\r
- RootBridgeDev->Handle,\r
- AcpiConfig\r
- );\r
- }\r
-\r
- //\r
- // Free acpi resource node\r
- //\r
- if (AcpiConfig != NULL) {\r
- FreePool (AcpiConfig);\r
- }\r
-\r
- if (EFI_ERROR (Status)) {\r
- //\r
- // Destroy all the resource tree\r
- //\r
- DestroyResourceTree (&IoPool);\r
- DestroyResourceTree (&Mem32Pool);\r
- DestroyResourceTree (&PMem32Pool);\r
- DestroyResourceTree (&Mem64Pool);\r
- DestroyResourceTree (&PMem64Pool);\r
- return Status;\r
- }\r
- }\r
-\r
- //\r
- // Notify pci bus driver starts to program the resource\r
- //\r
-\r
- Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeAllocateResources);\r
-\r
- if (!EFI_ERROR (Status)) {\r
- //\r
- // Allocation succeed, then continue the following\r
- //\r
- break;\r
- }\r
-\r
- //\r
- // If the resource allocation is unsuccessful, free resources on bridge\r
- //\r
-\r
- RootBridgeDev = NULL;\r
- RootBridgeHandle = 0;\r
-\r
- IoResStatus = EFI_RESOURCE_SATISFIED;\r
- Mem32ResStatus = EFI_RESOURCE_SATISFIED;\r
- PMem32ResStatus = EFI_RESOURCE_SATISFIED;\r
- Mem64ResStatus = EFI_RESOURCE_SATISFIED;\r
- PMem64ResStatus = EFI_RESOURCE_SATISFIED;\r
-\r
- while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
- //\r
- // Get RootBridg Device by handle\r
- //\r
- RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);\r
- if (RootBridgeDev == NULL) {\r
- return EFI_NOT_FOUND;\r
- }\r
-\r
- //\r
- // Get host bridge handle for status report\r
- //\r
- HandleExtendedData.Handle = RootBridgeDev->PciRootBridgeIo->ParentHandle;\r
-\r
- //\r
- // Get acpi resource node for all the resource types\r
- //\r
- AcpiConfig = NULL;\r
-\r
- Status = PciResAlloc->GetProposedResources (\r
- PciResAlloc,\r
- RootBridgeDev->Handle,\r
- &AcpiConfig\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- if (AcpiConfig != NULL) {\r
- //\r
- // Adjust resource allocation policy for each RB\r
- //\r
- GetResourceAllocationStatus (\r
- AcpiConfig,\r
- &IoResStatus,\r
- &Mem32ResStatus,\r
- &PMem32ResStatus,\r
- &Mem64ResStatus,\r
- &PMem64ResStatus\r
- );\r
- FreePool (AcpiConfig);\r
- }\r
- }\r
- //\r
- // End while\r
- //\r
-\r
- //\r
- // Raise the EFI_IOB_EC_RESOURCE_CONFLICT status code\r
- //\r
- //\r
- // It is very difficult to follow the spec here\r
- // Device path , Bar index can not be get here\r
- //\r
- ZeroMem (&AllocFailExtendedData, sizeof (AllocFailExtendedData));\r
-\r
- REPORT_STATUS_CODE_WITH_EXTENDED_DATA (\r
- EFI_PROGRESS_CODE,\r
- EFI_IO_BUS_PCI | EFI_IOB_EC_RESOURCE_CONFLICT,\r
- (VOID *) &AllocFailExtendedData,\r
- sizeof (AllocFailExtendedData)\r
- );\r
-\r
- Status = PciHostBridgeAdjustAllocation (\r
- &IoPool,\r
- &Mem32Pool,\r
- &PMem32Pool,\r
- &Mem64Pool,\r
- &PMem64Pool,\r
- IoResStatus,\r
- Mem32ResStatus,\r
- PMem32ResStatus,\r
- Mem64ResStatus,\r
- PMem64ResStatus\r
- );\r
-\r
- //\r
- // Destroy all the resource tree\r
- //\r
- DestroyResourceTree (&IoPool);\r
- DestroyResourceTree (&Mem32Pool);\r
- DestroyResourceTree (&PMem32Pool);\r
- DestroyResourceTree (&Mem64Pool);\r
- DestroyResourceTree (&PMem64Pool);\r
-\r
- NotifyPhase (PciResAlloc, EfiPciHostBridgeFreeResources);\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- ReAllocate = TRUE;\r
-\r
- }\r
- //\r
- // End main while\r
- //\r
-\r
- //\r
- // Raise the EFI_IOB_PCI_RES_ALLOC status code\r
- //\r
- REPORT_STATUS_CODE_WITH_EXTENDED_DATA (\r
- EFI_PROGRESS_CODE,\r
- EFI_IO_BUS_PCI | EFI_IOB_PCI_PC_RES_ALLOC,\r
- (VOID *) &HandleExtendedData,\r
- sizeof (HandleExtendedData)\r
- );\r
-\r
- //\r
- // Notify pci bus driver starts to program the resource\r
- //\r
- NotifyPhase (PciResAlloc, EfiPciHostBridgeSetResources);\r
-\r
- RootBridgeDev = NULL;\r
-\r
- RootBridgeHandle = 0;\r
-\r
- while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
-\r
- //\r
- // Get RootBridg Device by handle\r
- //\r
- RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);\r
-\r
- if (RootBridgeDev == NULL) {\r
- return EFI_NOT_FOUND;\r
- }\r
-\r
- //\r
- // Get acpi resource node for all the resource types\r
- //\r
- AcpiConfig = NULL;\r
- Status = PciResAlloc->GetProposedResources (\r
- PciResAlloc,\r
- RootBridgeDev->Handle,\r
- &AcpiConfig\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- //\r
- // Get the resource base by interpreting acpi resource node\r
- //\r
- //\r
- GetResourceBase (\r
- AcpiConfig,\r
- &IoBase,\r
- &Mem32Base,\r
- &PMem32Base,\r
- &Mem64Base,\r
- &PMem64Base\r
- );\r
-\r
- //\r
- // Process option rom for this root bridge\r
- //\r
- Status = ProcessOptionRom (RootBridgeDev, Mem32Base, RootBridgeDev->RomSize);\r
-\r
- //\r
- // Create the entire system resource map from the information collected by\r
- // enumerator. Several resource tree was created\r
- //\r
- Status = GetResourceMap (\r
- RootBridgeDev,\r
- &IoBridge,\r
- &Mem32Bridge,\r
- &PMem32Bridge,\r
- &Mem64Bridge,\r
- &PMem64Bridge,\r
- &IoPool,\r
- &Mem32Pool,\r
- &PMem32Pool,\r
- &Mem64Pool,\r
- &PMem64Pool\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- //\r
- // Program IO resources\r
- //\r
- ProgramResource (\r
- IoBase,\r
- IoBridge\r
- );\r
-\r
- //\r
- // Program Mem32 resources\r
- //\r
- ProgramResource (\r
- Mem32Base,\r
- Mem32Bridge\r
- );\r
-\r
- //\r
- // Program PMem32 resources\r
- //\r
- ProgramResource (\r
- PMem32Base,\r
- PMem32Bridge\r
- );\r
-\r
- //\r
- // Program Mem64 resources\r
- //\r
- ProgramResource (\r
- Mem64Base,\r
- Mem64Bridge\r
- );\r
-\r
- //\r
- // Program PMem64 resources\r
- //\r
- ProgramResource (\r
- PMem64Base,\r
- PMem64Bridge\r
- );\r
-\r
- if (AcpiConfig != NULL) {\r
- gBS->FreePool (AcpiConfig);\r
- }\r
- }\r
-\r
- //\r
- // Destroy all the resource tree\r
- //\r
- DestroyResourceTree (&IoPool);\r
- DestroyResourceTree (&Mem32Pool);\r
- DestroyResourceTree (&PMem32Pool);\r
- DestroyResourceTree (&Mem64Pool);\r
- DestroyResourceTree (&PMem64Pool);\r
-\r
- //\r
- // Notify the resource allocation phase is to end\r
- //\r
- NotifyPhase (PciResAlloc, EfiPciHostBridgeEndResourceAllocation);\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-\r
-EFI_STATUS\r
-PciScanBus (\r
- IN PCI_IO_DEVICE *Bridge,\r
- IN UINT8 StartBusNumber,\r
- OUT UINT8 *SubBusNumber,\r
- OUT UINT8 *PaddedBusRange\r
- )\r
-{\r
- if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
- return PciScanBus_WithHotPlugDeviceSupport (\r
- Bridge,\r
- StartBusNumber,\r
- SubBusNumber,\r
- PaddedBusRange\r
- );\r
- } else {\r
- return PciScanBus_WithoutHotPlugDeviceSupport (\r
- Bridge,\r
- StartBusNumber,\r
- SubBusNumber,\r
- PaddedBusRange\r
- );\r
- }\r
-}\r
-\r
-\r
-EFI_STATUS\r
-PciScanBus_WithoutHotPlugDeviceSupport (\r
- IN PCI_IO_DEVICE *Bridge,\r
- IN UINT8 StartBusNumber,\r
- OUT UINT8 *SubBusNumber,\r
- OUT UINT8 *PaddedBusRange\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- This routine is used to assign bus number to the given PCI bus system\r
-\r
-Arguments:\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-// TODO: Bridge - add argument and description to function comment\r
-// TODO: StartBusNumber - add argument and description to function comment\r
-// TODO: SubBusNumber - add argument and description to function comment\r
-// TODO: PaddedBusRange - add argument and description to function comment\r
-// TODO: EFI_DEVICE_ERROR - add return value to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
-{\r
- EFI_STATUS Status;\r
- PCI_TYPE00 Pci;\r
- UINT8 Device;\r
- UINT8 Func;\r
- UINT64 Address;\r
- UINTN SecondBus;\r
- UINT16 Register;\r
- PCI_IO_DEVICE *PciDevice;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
-\r
- PciRootBridgeIo = Bridge->PciRootBridgeIo;\r
- SecondBus = 0;\r
- Register = 0;\r
-\r
- ResetAllPpbBusReg (Bridge, StartBusNumber);\r
-\r
- for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
- for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {\r
-\r
- //\r
- // Check to see whether a pci device is present\r
- //\r
- Status = PciDevicePresent (\r
- PciRootBridgeIo,\r
- &Pci,\r
- StartBusNumber,\r
- Device,\r
- Func\r
- );\r
-\r
- if (!EFI_ERROR (Status) &&\r
- (IS_PCI_BRIDGE (&Pci) ||\r
- IS_CARDBUS_BRIDGE (&Pci))) {\r
-\r
- //\r
- // Get the bridge information\r
- //\r
- Status = PciSearchDevice (\r
- Bridge,\r
- &Pci,\r
- StartBusNumber,\r
- Device,\r
- Func,\r
- &PciDevice\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- (*SubBusNumber)++;\r
-\r
- SecondBus = (*SubBusNumber);\r
-\r
- Register = (UINT16) ((SecondBus << 8) | (UINT16) StartBusNumber);\r
-\r
- Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);\r
-\r
- Status = PciRootBridgeIoWrite (\r
- PciRootBridgeIo,\r
- &Pci,\r
- EfiPciWidthUint16,\r
- Address,\r
- 1,\r
- &Register\r
- );\r
-\r
- //\r
- // Initialize SubBusNumber to SecondBus\r
- //\r
- Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);\r
- Status = PciRootBridgeIoWrite (\r
- PciRootBridgeIo,\r
- &Pci,\r
- EfiPciWidthUint8,\r
- Address,\r
- 1,\r
- SubBusNumber\r
- );\r
- //\r
- // If it is PPB, resursively search down this bridge\r
- //\r
- if (IS_PCI_BRIDGE (&Pci)) {\r
- //\r
- // Temporarily initialize SubBusNumber to maximum bus number to ensure the\r
- // PCI configuration transaction to go through any PPB\r
- //\r
- Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);\r
- Register = 0xFF;\r
- Status = PciRootBridgeIoWrite (\r
- PciRootBridgeIo,\r
- &Pci,\r
- EfiPciWidthUint8,\r
- Address,\r
- 1,\r
- &Register\r
- );\r
-\r
- PreprocessController (\r
- PciDevice,\r
- PciDevice->BusNumber,\r
- PciDevice->DeviceNumber,\r
- PciDevice->FunctionNumber,\r
- EfiPciBeforeChildBusEnumeration\r
- );\r
-\r
- Status = PciScanBus (\r
- PciDevice,\r
- (UINT8) (SecondBus),\r
- SubBusNumber,\r
- PaddedBusRange\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- return EFI_DEVICE_ERROR;\r
- }\r
- }\r
-\r
- //\r
- // Set the current maximum bus number under the PPB\r
- //\r
-\r
- Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);\r
-\r
- Status = PciRootBridgeIoWrite (\r
- PciRootBridgeIo,\r
- &Pci,\r
- EfiPciWidthUint8,\r
- Address,\r
- 1,\r
- SubBusNumber\r
- );\r
-\r
- }\r
-\r
- if (Func == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {\r
-\r
- //\r
- // Skip sub functions, this is not a multi function device\r
- //\r
-\r
- Func = PCI_MAX_FUNC;\r
- }\r
- }\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-EFI_STATUS\r
-PciScanBus_WithHotPlugDeviceSupport (\r
- IN PCI_IO_DEVICE *Bridge,\r
- IN UINT8 StartBusNumber,\r
- OUT UINT8 *SubBusNumber,\r
- OUT UINT8 *PaddedBusRange\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- This routine is used to assign bus number to the given PCI bus system\r
-\r
-Arguments:\r
-\r
- Bridge - A pointer to the PCI_IO_DEVICE structure.\r
- StartBusNumber - The start bus number.\r
- SubBusNumber - A pointer to the sub bus number.\r
- PaddedBusRange - A pointer to the padded bus range.\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-// TODO: EFI_DEVICE_ERROR - add return value to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
-{\r
- EFI_STATUS Status;\r
- PCI_TYPE00 Pci;\r
- UINT8 Device;\r
- UINT8 Func;\r
- UINT64 Address;\r
- UINTN SecondBus;\r
- UINT16 Register;\r
- UINTN HpIndex;\r
- PCI_IO_DEVICE *PciDevice;\r
- EFI_EVENT Event;\r
- EFI_HPC_STATE State;\r
- UINT64 PciAddress;\r
- EFI_HPC_PADDING_ATTRIBUTES Attributes;\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
- UINT16 BusRange;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
- BOOLEAN BusPadding;\r
-\r
- PciRootBridgeIo = Bridge->PciRootBridgeIo;\r
- SecondBus = 0;\r
- Register = 0;\r
- State = 0;\r
- Attributes = (EFI_HPC_PADDING_ATTRIBUTES) 0;\r
- BusRange = 0;\r
-\r
- ResetAllPpbBusReg (Bridge, StartBusNumber);\r
-\r
- for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
- for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {\r
-\r
- //\r
- // Check to see whether a pci device is present\r
- //\r
- Status = PciDevicePresent (\r
- PciRootBridgeIo,\r
- &Pci,\r
- StartBusNumber,\r
- Device,\r
- Func\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- if (Func == 0) {\r
- //\r
- // Skip sub functions, this is not a multi function device\r
- //\r
- Func = PCI_MAX_FUNC;\r
- }\r
-\r
- continue;\r
- }\r
-\r
- //\r
- // Get the PCI device information\r
- //\r
- Status = PciSearchDevice (\r
- Bridge,\r
- &Pci,\r
- StartBusNumber,\r
- Device,\r
- Func,\r
- &PciDevice\r
- );\r
-\r
- ASSERT (!EFI_ERROR (Status));\r
-\r
- PciAddress = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0);\r
-\r
- if (!IS_PCI_BRIDGE (&Pci)) {\r
- //\r
- // PCI bridges will be called later\r
- // Here just need for PCI device or PCI to cardbus controller\r
- // EfiPciBeforeChildBusEnumeration for PCI Device Node\r
- //\r
- PreprocessController (\r
- PciDevice,\r
- PciDevice->BusNumber,\r
- PciDevice->DeviceNumber,\r
- PciDevice->FunctionNumber,\r
- EfiPciBeforeChildBusEnumeration\r
- );\r
- }\r
-\r
- //\r
- // For Pci Hotplug controller devcie only\r
- //\r
- if (gPciHotPlugInit != NULL) {\r
- //\r
- // Check if it is a Hotplug PCI controller\r
- //\r
- if (IsRootPciHotPlugController (PciDevice->DevicePath, &HpIndex)) {\r
-\r
- if (!gPciRootHpcData[HpIndex].Initialized) {\r
-\r
- Status = CreateEventForHpc (HpIndex, &Event);\r
-\r
- ASSERT (!EFI_ERROR (Status));\r
-\r
- Status = gPciHotPlugInit->InitializeRootHpc (\r
- gPciHotPlugInit,\r
- gPciRootHpcPool[HpIndex].HpcDevicePath,\r
- PciAddress,\r
- Event,\r
- &State\r
- );\r
-\r
- PreprocessController (\r
- PciDevice,\r
- PciDevice->BusNumber,\r
- PciDevice->DeviceNumber,\r
- PciDevice->FunctionNumber,\r
- EfiPciBeforeChildBusEnumeration\r
- );\r
- continue;\r
- }\r
- }\r
- }\r
-\r
- if (IS_PCI_BRIDGE (&Pci) || IS_CARDBUS_BRIDGE (&Pci)) {\r
- //\r
- // For PPB\r
- // Get the bridge information\r
- //\r
- BusPadding = FALSE;\r
- if (gPciHotPlugInit != NULL) {\r
-\r
- if (IsRootPciHotPlugBus (PciDevice->DevicePath, &HpIndex)) {\r
-\r
- //\r
- // If it is initialized, get the padded bus range\r
- //\r
- Status = gPciHotPlugInit->GetResourcePadding (\r
- gPciHotPlugInit,\r
- gPciRootHpcPool[HpIndex].HpbDevicePath,\r
- PciAddress,\r
- &State,\r
- (VOID **) &Descriptors,\r
- &Attributes\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- BusRange = 0;\r
- Status = PciGetBusRange (\r
- &Descriptors,\r
- NULL,\r
- NULL,\r
- &BusRange\r
- );\r
-\r
- gBS->FreePool (Descriptors);\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- BusPadding = TRUE;\r
- }\r
- }\r
-\r
- (*SubBusNumber)++;\r
- SecondBus = *SubBusNumber;\r
-\r
- Register = (UINT16) ((SecondBus << 8) | (UINT16) StartBusNumber);\r
- Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);\r
-\r
- Status = PciRootBridgeIoWrite (\r
- PciRootBridgeIo,\r
- &Pci,\r
- EfiPciWidthUint16,\r
- Address,\r
- 1,\r
- &Register\r
- );\r
-\r
-\r
- //\r
- // If it is PPB, resursively search down this bridge\r
- //\r
- if (IS_PCI_BRIDGE (&Pci)) {\r
-\r
- //\r
- // Initialize SubBusNumber to Maximum bus number\r
- //\r
- Register = 0xFF;\r
- Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);\r
- Status = PciRootBridgeIoWrite (\r
- PciRootBridgeIo,\r
- &Pci,\r
- EfiPciWidthUint8,\r
- Address,\r
- 1,\r
- &Register\r
- );\r
-\r
- //\r
- // Nofify EfiPciBeforeChildBusEnumeration for PCI Brige\r
- //\r
- PreprocessController (\r
- PciDevice,\r
- PciDevice->BusNumber,\r
- PciDevice->DeviceNumber,\r
- PciDevice->FunctionNumber,\r
- EfiPciBeforeChildBusEnumeration\r
- );\r
-\r
- Status = PciScanBus (\r
- PciDevice,\r
- (UINT8) (SecondBus),\r
- SubBusNumber,\r
- PaddedBusRange\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- return EFI_DEVICE_ERROR;\r
- }\r
- }\r
-\r
- if (BusPadding) {\r
- //\r
- // Ensure the device is enabled and initialized\r
- //\r
- if ((Attributes == EfiPaddingPciRootBridge) &&\r
- (State & EFI_HPC_STATE_ENABLED) &&\r
- (State & EFI_HPC_STATE_INITIALIZED) ) {\r
- *PaddedBusRange = (UINT8) ((UINT8) (BusRange) +*PaddedBusRange);\r
- } else {\r
- *SubBusNumber = (UINT8) ((UINT8) (BusRange) +*SubBusNumber);\r
- }\r
- }\r
-\r
- //\r
- // Set the current maximum bus number under the PPB\r
- //\r
- Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);\r
-\r
- Status = PciRootBridgeIoWrite (\r
- PciRootBridgeIo,\r
- &Pci,\r
- EfiPciWidthUint8,\r
- Address,\r
- 1,\r
- SubBusNumber\r
- );\r
- }\r
-\r
- if (Func == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {\r
-\r
- //\r
- // Skip sub functions, this is not a multi function device\r
- //\r
- Func = PCI_MAX_FUNC;\r
- }\r
-\r
- }\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-EFI_STATUS\r
-PciRootBridgeP2CProcess (\r
- IN PCI_IO_DEVICE *Bridge\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Process Option Rom on this host bridge\r
-\r
-Arguments:\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-// TODO: Bridge - add argument and description to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
-{\r
- LIST_ENTRY *CurrentLink;\r
- PCI_IO_DEVICE *Temp;\r
- EFI_HPC_STATE State;\r
- UINT64 PciAddress;\r
- EFI_STATUS Status;\r
-\r
- CurrentLink = Bridge->ChildList.ForwardLink;\r
-\r
- while (CurrentLink && CurrentLink != &Bridge->ChildList) {\r
-\r
- Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);\r
-\r
- if (IS_CARDBUS_BRIDGE (&Temp->Pci)) {\r
-\r
- if (gPciHotPlugInit && Temp->Allocated) {\r
-\r
- //\r
- // Raise the EFI_IOB_PCI_HPC_INIT status code\r
- //\r
- REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
- EFI_PROGRESS_CODE,\r
- EFI_IO_BUS_PCI | EFI_IOB_PCI_PC_HPC_INIT,\r
- Temp->DevicePath\r
- );\r
-\r
- PciAddress = EFI_PCI_ADDRESS (Temp->BusNumber, Temp->DeviceNumber, Temp->FunctionNumber, 0);\r
- Status = gPciHotPlugInit->InitializeRootHpc (\r
- gPciHotPlugInit,\r
- Temp->DevicePath,\r
- PciAddress,\r
- NULL,\r
- &State\r
- );\r
-\r
- if (!EFI_ERROR (Status)) {\r
- Status = PciBridgeEnumerator (Temp);\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
- }\r
-\r
- CurrentLink = CurrentLink->ForwardLink;\r
- continue;\r
-\r
- }\r
- }\r
-\r
- if (!IsListEmpty (&Temp->ChildList)) {\r
- Status = PciRootBridgeP2CProcess (Temp);\r
- }\r
-\r
- CurrentLink = CurrentLink->ForwardLink;\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-EFI_STATUS\r
-PciHostBridgeP2CProcess (\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-// TODO: PciResAlloc - add argument and description to function comment\r
-// TODO: EFI_NOT_FOUND - add return value to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
-{\r
- EFI_HANDLE RootBridgeHandle;\r
- PCI_IO_DEVICE *RootBridgeDev;\r
- EFI_STATUS Status;\r
-\r
- if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
- return EFI_SUCCESS;\r
- }\r
-\r
- RootBridgeHandle = NULL;\r
-\r
- while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
-\r
- //\r
- // Get RootBridg Device by handle\r
- //\r
- RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);\r
-\r
- if (RootBridgeDev == NULL) {\r
- return EFI_NOT_FOUND;\r
- }\r
-\r
- Status = PciRootBridgeP2CProcess (RootBridgeDev);\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-EFI_STATUS\r
-PciHostBridgeEnumerator (\r
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- This function is used to enumerate the entire host bridge\r
- in a given platform\r
-\r
-Arguments:\r
-\r
- PciResAlloc - A pointer to the resource allocate protocol.\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-// TODO: EFI_OUT_OF_RESOURCES - add return value to function comment\r
-// TODO: EFI_OUT_OF_RESOURCES - add return value to function comment\r
-// TODO: EFI_OUT_OF_RESOURCES - add return value to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
-{\r
- EFI_HANDLE RootBridgeHandle;\r
- PCI_IO_DEVICE *RootBridgeDev;\r
- EFI_STATUS Status;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
- UINT16 MinBus;\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
-\r
- InitializeHotPlugSupport ();\r
-\r
- //\r
- // Notify the bus allocation phase is about to start\r
- //\r
- NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginBusAllocation);\r
-\r
- RootBridgeHandle = NULL;\r
- while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
-\r
- //\r
- // if a root bridge instance is found, create root bridge device for it\r
- //\r
-\r
- RootBridgeDev = CreateRootBridge (RootBridgeHandle);\r
-\r
- if (RootBridgeDev == NULL) {\r
- return EFI_OUT_OF_RESOURCES;\r
- }\r
-\r
- //\r
- // Enumerate all the buses under this root bridge\r
- //\r
-\r
- Status = PciRootBridgeEnumerator (\r
- PciResAlloc,\r
- RootBridgeDev\r
- );\r
-\r
- DestroyRootBridge (RootBridgeDev);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
- }\r
-\r
- //\r
- // Notify the bus allocation phase is finished for the first time\r
- //\r
- NotifyPhase (PciResAlloc, EfiPciHostBridgeEndBusAllocation);\r
-\r
- if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
-\r
- if (gPciHotPlugInit != NULL) {\r
- //\r
- // Wait for all HPC initialized\r
- //\r
- Status = AllRootHPCInitialized (STALL_1_SECOND * 15);\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- //\r
- // Notify the bus allocation phase is about to start for the 2nd time\r
- //\r
- NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginBusAllocation);\r
-\r
- RootBridgeHandle = NULL;\r
- while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
-\r
- //\r
- // if a root bridge instance is found, create root bridge device for it\r
- //\r
-\r
- RootBridgeDev = CreateRootBridge (RootBridgeHandle);\r
-\r
- if (RootBridgeDev == NULL) {\r
- return EFI_OUT_OF_RESOURCES;\r
- }\r
-\r
- //\r
- // Enumerate all the buses under this root bridge\r
- //\r
-\r
- Status = PciRootBridgeEnumerator (\r
- PciResAlloc,\r
- RootBridgeDev\r
- );\r
-\r
- DestroyRootBridge (RootBridgeDev);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
- }\r
-\r
- //\r
- // Notify the bus allocation phase is to end for the 2nd time\r
- //\r
- NotifyPhase (PciResAlloc, EfiPciHostBridgeEndBusAllocation);\r
- }\r
- }\r
-\r
- //\r
- // Notify the resource allocation phase is to start\r
- //\r
- NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginResourceAllocation);\r
-\r
- RootBridgeHandle = NULL;\r
- while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
-\r
- //\r
- // if a root bridge instance is found, create root bridge device for it\r
- //\r
-\r
- RootBridgeDev = CreateRootBridge (RootBridgeHandle);\r
-\r
- if (RootBridgeDev == NULL) {\r
- return EFI_OUT_OF_RESOURCES;\r
- }\r
-\r
- Status = StartManagingRootBridge (RootBridgeDev);\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- PciRootBridgeIo = RootBridgeDev->PciRootBridgeIo;\r
- Status = PciRootBridgeIo->Configuration (PciRootBridgeIo, (VOID **) &Descriptors);\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- Status = PciGetBusRange (&Descriptors, &MinBus, NULL, NULL);\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- //\r
- // Determine root bridge attribute by calling interface of Pcihostbridge\r
- // protocol\r
- //\r
- DetermineRootBridgeAttributes (\r
- PciResAlloc,\r
- RootBridgeDev\r
- );\r
-\r
- //\r
- // Collect all the resource information under this root bridge\r
- // A database that records all the information about pci device subject to this\r
- // root bridge will then be created\r
- //\r
- Status = PciPciDeviceInfoCollector (\r
- RootBridgeDev,\r
- (UINT8) MinBus\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- InsertRootBridge (RootBridgeDev);\r
-\r
- //\r
- // Record the hostbridge handle\r
- //\r
- AddHostBridgeEnumerator (RootBridgeDev->PciRootBridgeIo->ParentHandle);\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Read PCI device configuration register by specified address.\r
-\r
- This function check the incompatiblilites on PCI device. Return the register\r
- value.\r
-\r
- @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param PciIo A pointer to EFI_PCI_PROTOCOL.\r
- @param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.\r
- @param Width Signifies the width of the memory operations.\r
- @Param Address The address within the PCI configuration space for the PCI controller.\r
- @param Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-\r
-**/\r
-STATIC\r
-EFI_STATUS\r
-ReadConfigData (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, OPTIONAL\r
- IN EFI_PCI_IO_PROTOCOL *PciIo, OPTIONAL\r
- IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,\r
- IN UINT64 Width,\r
- IN UINT64 Address,\r
- IN OUT VOID *Buffer\r
- )\r
-{\r
- EFI_STATUS Status;\r
- UINT64 AccessWidth;\r
- EFI_PCI_REGISTER_ACCESS_DATA *PciRegisterAccessData;\r
- UINT64 AccessAddress;\r
- UINTN Stride;\r
- UINT64 TempBuffer;\r
- UINT8 *Pointer;\r
-\r
- ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL));\r
-\r
- if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT) {\r
- //\r
- // check access compatibility at first time\r
- //\r
- Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_READ, Address & 0xff, Width, &PciRegisterAccessData);\r
-\r
- if (Status == EFI_SUCCESS) {\r
- //\r
- // there exist incompatibility on this operation\r
- //\r
- AccessWidth = Width;\r
-\r
- if (PciRegisterAccessData->Width != VALUE_NOCARE) {\r
- AccessWidth = PciRegisterAccessData->Width;\r
- }\r
-\r
- AccessAddress = Address & ~((1 << AccessWidth) - 1);\r
-\r
- TempBuffer = 0;\r
- Stride = 0;\r
- Pointer = (UINT8 *) &TempBuffer;\r
-\r
- while (1) {\r
-\r
- if (PciRootBridgeIo != NULL) {\r
- Status = PciRootBridgeIo->Pci.Read (\r
- PciRootBridgeIo,\r
- (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) AccessWidth,\r
- AccessAddress,\r
- 1,\r
- Pointer\r
- );\r
- } else if (PciIo != NULL) {\r
- Status = PciIo->Pci.Read (\r
- PciIo,\r
- (EFI_PCI_IO_PROTOCOL_WIDTH) AccessWidth,\r
- (UINT32) AccessAddress,\r
- 1,\r
- Pointer\r
- );\r
- }\r
-\r
- if (Status != EFI_SUCCESS) {\r
- return Status;\r
- }\r
-\r
- Stride = 1 << AccessWidth;\r
- AccessAddress += Stride;\r
- if (AccessAddress >= (Address + (1 << Width))) {\r
- //\r
- // if all datas have been read, exist\r
- //\r
- break;\r
- }\r
-\r
- Pointer += Stride;\r
-\r
- if ((AccessAddress & 0xff) < PciRegisterAccessData->EndOffset) {\r
- //\r
- // if current offset doesn't reach the end\r
- //\r
- continue;\r
- }\r
-\r
- FreePool (PciRegisterAccessData);\r
-\r
- //\r
- // continue checking access incompatibility\r
- //\r
- Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_READ, AccessAddress & 0xff, AccessWidth, &PciRegisterAccessData);\r
- if (Status == EFI_SUCCESS) {\r
- if (PciRegisterAccessData->Width != VALUE_NOCARE) {\r
- AccessWidth = PciRegisterAccessData->Width;\r
- }\r
- }\r
- }\r
-\r
- FreePool (PciRegisterAccessData);\r
-\r
- switch (Width) {\r
- case EfiPciWidthUint8:\r
- * (UINT8 *) Buffer = (UINT8) TempBuffer;\r
- break;\r
- case EfiPciWidthUint16:\r
- * (UINT16 *) Buffer = (UINT16) TempBuffer;\r
- break;\r
- case EfiPciWidthUint32:\r
- * (UINT32 *) Buffer = (UINT32) TempBuffer;\r
- break;\r
- default:\r
- return EFI_UNSUPPORTED;\r
- }\r
-\r
- return Status;\r
- }\r
- }\r
- //\r
- // AccessWidth incompatible check not supportted\r
- // or, there doesn't exist incompatibility on this operation\r
- //\r
- if (PciRootBridgeIo != NULL) {\r
- Status = PciRootBridgeIo->Pci.Read (\r
- PciRootBridgeIo,\r
- (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
- Address,\r
- 1,\r
- Buffer\r
- );\r
-\r
- } else {\r
- Status = PciIo->Pci.Read (\r
- PciIo,\r
- (EFI_PCI_IO_PROTOCOL_WIDTH) Width,\r
- (UINT32) Address,\r
- 1,\r
- Buffer\r
- );\r
- }\r
-\r
- return Status;\r
-}\r
-\r
-/**\r
- Update register value by checking PCI device incompatibility.\r
-\r
- This function check register value incompatibilites on PCI device. Return the register\r
- value.\r
-\r
- @param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.\r
- @param AccessType Access type, READ or WRITE.\r
- @Param Address The address within the PCI configuration space.\r
- @param Buffer Store the register data.\r
-\r
- @retval EFI_SUCCESS The data has been updated.\r
-\r
-**/\r
-STATIC\r
-EFI_STATUS\r
-UpdateConfigData (\r
- IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,\r
- IN UINT64 AccessType,\r
- IN UINT64 Width,\r
- IN UINT64 Address,\r
- IN OUT VOID *Buffer\r
-)\r
-{\r
- EFI_STATUS Status;\r
- EFI_PCI_REGISTER_VALUE_DATA *PciRegisterData;\r
- UINT32 AndValue;\r
- UINT32 OrValue;\r
- UINT32 TempValue;\r
-\r
- //\r
- // check register value incompatibility\r
- //\r
- Status = PciRegisterUpdateCheck (PciDeviceInfo, AccessType, Address & 0xff, &PciRegisterData);\r
-\r
- if (Status == EFI_SUCCESS) {\r
-\r
- AndValue = ((UINT32) PciRegisterData->AndValue) >> (((UINT8) Address & 0x3) * 8);\r
- OrValue = ((UINT32) PciRegisterData->OrValue) >> (((UINT8) Address & 0x3) * 8);\r
-\r
- TempValue = * (UINT32 *) Buffer;\r
- if (PciRegisterData->AndValue != VALUE_NOCARE) {\r
- TempValue &= AndValue;\r
- }\r
- if (PciRegisterData->OrValue != VALUE_NOCARE) {\r
- TempValue |= OrValue;\r
- }\r
-\r
- switch (Width) {\r
- case EfiPciWidthUint8:\r
- *(UINT8 *)Buffer = (UINT8) TempValue;\r
- break;\r
-\r
- case EfiPciWidthUint16:\r
- *(UINT16 *)Buffer = (UINT16) TempValue;\r
- break;\r
- case EfiPciWidthUint32:\r
- *(UINT32 *)Buffer = TempValue;\r
- break;\r
-\r
- default:\r
- return EFI_UNSUPPORTED;\r
- }\r
-\r
- FreePool (PciRegisterData);\r
- }\r
-\r
- return Status;\r
-}\r
-\r
-/**\r
- Write PCI device configuration register by specified address.\r
-\r
- This function check the incompatiblilites on PCI device, and write date\r
- into register.\r
-\r
- @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param PciIo A pointer to EFI_PCI_PROTOCOL.\r
- @param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.\r
- @param Width Signifies the width of the memory operations.\r
- @Param Address The address within the PCI configuration space for the PCI controller.\r
- @param Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-\r
-**/\r
-STATIC\r
-EFI_STATUS\r
-WriteConfigData (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, OPTIONAL\r
- IN EFI_PCI_IO_PROTOCOL *PciIo, OPTIONAL\r
- IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,\r
- IN UINT64 Width,\r
- IN UINT64 Address,\r
- IN VOID *Buffer\r
- )\r
-{\r
- EFI_STATUS Status;\r
- UINT64 AccessWidth;\r
- EFI_PCI_REGISTER_ACCESS_DATA *PciRegisterAccessData;\r
- UINT64 AccessAddress;\r
- UINTN Stride;\r
- UINT8 *Pointer;\r
- UINT64 Data;\r
- UINTN Shift;\r
-\r
- ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL));\r
-\r
- if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT) {\r
- //\r
- // check access compatibility at first time\r
- //\r
- Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_WRITE, Address & 0xff, Width, &PciRegisterAccessData);\r
-\r
- if (Status == EFI_SUCCESS) {\r
- //\r
- // there exist incompatibility on this operation\r
- //\r
- AccessWidth = Width;\r
-\r
- if (PciRegisterAccessData->Width != VALUE_NOCARE) {\r
- AccessWidth = PciRegisterAccessData->Width;\r
- }\r
-\r
- AccessAddress = Address & ~((1 << AccessWidth) - 1);\r
-\r
- Stride = 0;\r
- Pointer = (UINT8 *) &Buffer;\r
- Data = * (UINT64 *) Buffer;\r
-\r
- while (1) {\r
-\r
- if (AccessWidth > Width) {\r
- //\r
- // if actual access width is larger than orignal one, additional data need to be read back firstly\r
- //\r
- Status = ReadConfigData (PciRootBridgeIo, PciIo, PciDeviceInfo, AccessWidth, AccessAddress, &Data);\r
- if (Status != EFI_SUCCESS) {\r
- return Status;\r
- }\r
-\r
- //\r
- // check data read incompatibility\r
- //\r
- UpdateConfigData (PciDeviceInfo, PCI_REGISTER_READ, AccessWidth, AccessAddress & 0xff, &Data);\r
-\r
- Shift = (UINTN)(Address - AccessAddress) * 8;\r
- switch (Width) {\r
- case EfiPciWidthUint8:\r
- Data = (* (UINT8 *) Buffer) << Shift | (Data & ~(0xff << Shift));\r
- break;\r
-\r
- case EfiPciWidthUint16:\r
- Data = (* (UINT16 *) Buffer) << Shift | (Data & ~(0xffff << Shift));\r
- break;\r
- }\r
-\r
- //\r
- // check data write incompatibility\r
- //\r
- UpdateConfigData (PciDeviceInfo, PCI_REGISTER_WRITE, AccessWidth, MultU64x32 (AccessAddress, 0xff), &Data);\r
- }\r
-\r
- if (PciRootBridgeIo != NULL) {\r
- Status = PciRootBridgeIo->Pci.Write (\r
- PciRootBridgeIo,\r
- (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) AccessWidth,\r
- AccessAddress,\r
- 1,\r
- &Data\r
- );\r
- } else {\r
- Status = PciIo->Pci.Write (\r
- PciIo,\r
- (EFI_PCI_IO_PROTOCOL_WIDTH) AccessWidth,\r
- (UINT32) AccessAddress,\r
- 1,\r
- &Data\r
- );\r
- }\r
-\r
- if (Status != EFI_SUCCESS) {\r
- return Status;\r
- }\r
-\r
- Data = RShiftU64 (Data, ((1 << AccessWidth) * 8));\r
-\r
- Stride = 1 << AccessWidth;\r
- AccessAddress += Stride;\r
- if (AccessAddress >= (Address + (1 << Width))) {\r
- //\r
- // if all datas have been written, exist\r
- //\r
- break;\r
- }\r
-\r
- Pointer += Stride;\r
-\r
- if ((AccessAddress & 0xff) < PciRegisterAccessData->EndOffset) {\r
- //\r
- // if current offset doesn't reach the end\r
- //\r
- continue;\r
- }\r
-\r
- FreePool (PciRegisterAccessData);\r
-\r
- //\r
- // continue checking access incompatibility\r
- //\r
- Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_WRITE, AccessAddress & 0xff, AccessWidth, &PciRegisterAccessData);\r
- if (Status == EFI_SUCCESS) {\r
- if (PciRegisterAccessData->Width != VALUE_NOCARE) {\r
- AccessWidth = PciRegisterAccessData->Width;\r
- }\r
- }\r
- };\r
-\r
- FreePool (PciRegisterAccessData);\r
-\r
- return Status;\r
- }\r
-\r
- }\r
- //\r
- // AccessWidth incompatible check not supportted\r
- // or, there doesn't exist incompatibility on this operation\r
- //\r
- if (PciRootBridgeIo != NULL) {\r
- Status = PciRootBridgeIo->Pci.Write (\r
- PciRootBridgeIo,\r
- (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
- Address,\r
- 1,\r
- Buffer\r
- );\r
- } else {\r
- Status = PciIo->Pci.Write (\r
- PciIo,\r
- (EFI_PCI_IO_PROTOCOL_WIDTH) Width,\r
- (UINT32) Address,\r
- 1,\r
- Buffer\r
- );\r
- }\r
-\r
- return Status;\r
-}\r
-\r
-/**\r
- Abstract PCI device device information.\r
-\r
- @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param PciIo A pointer to EFI_PCI_PROTOCOL.\r
- @param Pci A pointer to PCI_TYPE00.\r
- @Param Address The address within the PCI configuration space for the PCI controller.\r
- @param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.\r
-\r
- @retval EFI_SUCCESS Pci device device information has been abstracted.\r
-\r
-**/\r
-STATIC\r
-EFI_STATUS\r
-GetPciDeviceDeviceInfo (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, OPTIONAL\r
- IN EFI_PCI_IO_PROTOCOL *PciIo, OPTIONAL\r
- IN PCI_TYPE00 *Pci, OPTIONAL\r
- IN UINT64 Address, OPTIONAL\r
- OUT EFI_PCI_DEVICE_INFO *PciDeviceInfo\r
-)\r
-{\r
- EFI_STATUS Status;\r
- UINT64 PciAddress;\r
- UINT32 PciConfigData;\r
- PCI_IO_DEVICE *PciIoDevice;\r
-\r
- ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL));\r
-\r
- if (PciIo != NULL) {\r
- PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciIo);\r
-\r
- //\r
- // get pointer to PCI_TYPE00 from PciIoDevice\r
- //\r
- Pci = &PciIoDevice->Pci;\r
- }\r
-\r
- if (Pci == NULL) {\r
- //\r
- // while PCI_TYPE00 hasn't been gotten, read PCI device device information directly\r
- //\r
- PciAddress = Address & 0xffffffffffffff00ULL;\r
- Status = PciRootBridgeIo->Pci.Read (\r
- PciRootBridgeIo,\r
- EfiPciWidthUint32,\r
- PciAddress,\r
- 1,\r
- &PciConfigData\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- if ((PciConfigData & 0xffff) == 0xffff) {\r
- return EFI_NOT_FOUND;\r
- }\r
-\r
- PciDeviceInfo->VendorID = PciConfigData & 0xffff;\r
- PciDeviceInfo->DeviceID = PciConfigData >> 16;\r
-\r
- Status = PciRootBridgeIo->Pci.Read (\r
- PciRootBridgeIo,\r
- EfiPciWidthUint32,\r
- PciAddress + 8,\r
- 1,\r
- &PciConfigData\r
- );\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- PciDeviceInfo->RevisionID = PciConfigData & 0xf;\r
-\r
- Status = PciRootBridgeIo->Pci.Read (\r
- PciRootBridgeIo,\r
- EfiPciWidthUint32,\r
- PciAddress + 0x2c,\r
- 1,\r
- &PciConfigData\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- PciDeviceInfo->SubsystemVendorID = PciConfigData & 0xffff;\r
- PciDeviceInfo->SubsystemID = PciConfigData >> 16;\r
-\r
- } else {\r
- PciDeviceInfo->VendorID = Pci->Hdr.VendorId;\r
- PciDeviceInfo->DeviceID = Pci->Hdr.DeviceId;\r
- PciDeviceInfo->RevisionID = Pci->Hdr.RevisionID;\r
- PciDeviceInfo->SubsystemVendorID = Pci->Device.SubsystemVendorID;\r
- PciDeviceInfo->SubsystemID = Pci->Device.SubsystemID;\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Read PCI configuration space with incompatibility check.\r
-\r
- @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param PciIo A pointer to the EFI_PCI_IO_PROTOCOL.\r
- @param Pci A pointer to PCI_TYPE00.\r
- @param Width Signifies the width of the memory operations.\r
- @Param Address The address within the PCI configuration space for the PCI controller.\r
- @param Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-\r
-**/\r
-STATIC\r
-EFI_STATUS\r
-PciIncompatibilityCheckRead (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, OPTIONAL\r
- IN EFI_PCI_IO_PROTOCOL *PciIo, OPTIONAL\r
- IN PCI_TYPE00 *Pci, OPTIONAL\r
- IN UINTN Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN OUT VOID *Buffer\r
-)\r
-{\r
- EFI_STATUS Status;\r
- EFI_PCI_DEVICE_INFO PciDeviceInfo;\r
- UINT32 Stride;\r
-\r
- ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL));\r
-\r
- //\r
- // get PCI device device information\r
- //\r
- Status = GetPciDeviceDeviceInfo (PciRootBridgeIo, PciIo, Pci, Address, &PciDeviceInfo);\r
- if (Status != EFI_SUCCESS) {\r
- return Status;\r
- }\r
-\r
- Stride = 1 << Width;\r
-\r
- for (; Count > 0; Count--, Address += Stride, Buffer = (UINT8 *)Buffer + Stride) {\r
-\r
- //\r
- // read configuration register\r
- //\r
- Status = ReadConfigData (PciRootBridgeIo, PciIo, &PciDeviceInfo, (UINT64) Width, Address, Buffer);\r
-\r
- if (Status != EFI_SUCCESS) {\r
- return Status;\r
- }\r
-\r
- //\r
- // update the data read from configuration register\r
- //\r
- if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT) {\r
- UpdateConfigData (&PciDeviceInfo, PCI_REGISTER_READ, Width, Address & 0xff, Buffer);\r
- }\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Write PCI configuration space with incompatibility check.\r
-\r
- @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param PciIo A pointer to the EFI_PCI_IO_PROTOCOL.\r
- @param Pci A pointer to PCI_TYPE00.\r
- @param Width Signifies the width of the memory operations.\r
- @Param Address The address within the PCI configuration space for the PCI controller.\r
- @param Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-\r
-**/\r
-STATIC\r
-EFI_STATUS\r
-PciIncompatibilityCheckWrite (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, OPTIONAL\r
- IN EFI_PCI_IO_PROTOCOL *PciIo, OPTIONAL\r
- IN PCI_TYPE00 *Pci, OPTIONAL\r
- IN UINTN Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN OUT VOID *Buffer\r
-)\r
-{\r
- EFI_STATUS Status;\r
- EFI_PCI_DEVICE_INFO PciDeviceInfo;\r
- UINT32 Stride;\r
- UINT64 Data;\r
-\r
- ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL));\r
-\r
- //\r
- // get PCI device device information\r
- //\r
- Status = GetPciDeviceDeviceInfo (PciRootBridgeIo, PciIo, Pci, Address, &PciDeviceInfo);\r
- if (Status != EFI_SUCCESS) {\r
- return Status;\r
- }\r
-\r
- Stride = 1 << Width;\r
-\r
- for (; Count > 0; Count--, Address += Stride, Buffer = (UINT8 *) Buffer + Stride) {\r
-\r
- Data = 0;\r
-\r
- switch (Width) {\r
- case EfiPciWidthUint8:\r
- Data = * (UINT8 *) Buffer;\r
- break;\r
- case EfiPciWidthUint16:\r
- Data = * (UINT16 *) Buffer;\r
- break;\r
-\r
- case EfiPciWidthUint32:\r
- Data = * (UINT32 *) Buffer;\r
- break;\r
-\r
- default:\r
- return EFI_UNSUPPORTED;\r
- }\r
-\r
- //\r
- // update the data writen into configuration register\r
- //\r
- if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT) {\r
- UpdateConfigData (&PciDeviceInfo, PCI_REGISTER_WRITE, Width, Address & 0xff, &Data);\r
- }\r
-\r
- //\r
- // write configuration register\r
- //\r
- Status = WriteConfigData (PciRootBridgeIo, PciIo, &PciDeviceInfo, Width, Address, &Data);\r
-\r
- if (Status != EFI_SUCCESS) {\r
- return Status;\r
- }\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Read PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param Pci A pointer to PCI_TYPE00.\r
- @param Width Signifies the width of the memory operations.\r
- @Param Address The address within the PCI configuration space for the PCI controller.\r
- @param Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-\r
-**/\r
-EFI_STATUS\r
-PciRootBridgeIoRead (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
- IN PCI_TYPE00 *Pci, OPTIONAL\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN OUT VOID *Buffer\r
- )\r
-{\r
- if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_READ_SUPPORT) {\r
- //\r
- // if PCI incompatibility check enabled\r
- //\r
- return PciIncompatibilityCheckRead (\r
- PciRootBridgeIo,\r
- NULL,\r
- Pci,\r
- (UINTN) Width,\r
- Address,\r
- Count,\r
- Buffer\r
- );\r
- } else {\r
- return PciRootBridgeIo->Pci.Read (\r
- PciRootBridgeIo,\r
- Width,\r
- Address,\r
- Count,\r
- Buffer\r
- );\r
- }\r
-}\r
-\r
-/**\r
- Write PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param Pci A pointer to PCI_TYPE00.\r
- @param Width Signifies the width of the memory operations.\r
- @Param Address The address within the PCI configuration space for the PCI controller.\r
- @param Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-\r
-**/\r
-EFI_STATUS\r
-PciRootBridgeIoWrite (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
- IN PCI_TYPE00 *Pci,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN OUT VOID *Buffer\r
- )\r
-{\r
- if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_WRITE_SUPPORT) {\r
- //\r
- // if PCI incompatibility check enabled\r
- //\r
- return PciIncompatibilityCheckWrite (\r
- PciRootBridgeIo,\r
- NULL,\r
- Pci,\r
- Width,\r
- Address,\r
- Count,\r
- Buffer\r
- );\r
-\r
- } else {\r
- return PciRootBridgeIo->Pci.Write (\r
- PciRootBridgeIo,\r
- Width,\r
- Address,\r
- Count,\r
- Buffer\r
- );\r
- }\r
-}\r
-\r
-/**\r
- Read PCI configuration space through EFI_PCI_IO_PROTOCOL.\r
-\r
- @param PciIo A pointer to the EFI_PCI_O_PROTOCOL.\r
- @param Width Signifies the width of the memory operations.\r
- @Param Address The address within the PCI configuration space for the PCI controller.\r
- @param Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-\r
-**/\r
-EFI_STATUS\r
-PciIoRead (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
- IN UINT32 Address,\r
- IN UINTN Count,\r
- IN OUT VOID *Buffer\r
- )\r
-{\r
- if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_READ_SUPPORT) {\r
- //\r
- // if PCI incompatibility check enabled\r
- //\r
- return PciIncompatibilityCheckRead (\r
- NULL,\r
- PciIo,\r
- NULL,\r
- (UINTN) Width,\r
- Address,\r
- Count,\r
- Buffer\r
- );\r
- } else {\r
- return PciIo->Pci.Read (\r
- PciIo,\r
- Width,\r
- Address,\r
- Count,\r
- Buffer\r
- );\r
- }\r
-}\r
-\r
-/**\r
- Write PCI configuration space through EFI_PCI_IO_PROTOCOL.\r
-\r
- @param PciIo A pointer to the EFI_PCI_O_PROTOCOL.\r
- @param Width Signifies the width of the memory operations.\r
- @Param Address The address within the PCI configuration space for the PCI controller.\r
- @param Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-\r
-**/\r
-EFI_STATUS\r
-PciIoWrite (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
- IN UINT32 Address,\r
- IN UINTN Count,\r
- IN OUT VOID *Buffer\r
- )\r
-{\r
- if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_WRITE_SUPPORT) {\r
-\r
- //\r
- // if PCI incompatibility check enabled\r
- //\r
- return PciIncompatibilityCheckWrite (\r
- NULL,\r
- PciIo,\r
- NULL,\r
- Width,\r
- Address,\r
- Count,\r
- Buffer\r
- );\r
-\r
- } else {\r
- return PciIo->Pci.Write (\r
- PciIo,\r
- Width,\r
- Address,\r
- Count,\r
- Buffer\r
- );\r
- }\r
-}\r
projects / mirror_edk2.git / blobdiff