clean up the un-suitable ';' location when declaring the functions.

[mirror_edk2.git] / IntelFrameworkModulePkg / Bus / Pci / PciBusDxe / PciIo.h

diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciIo.h b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciIo.h
index 216ee402fd5cc6a5fc1a89150a44853b03cbeec3..f1ac6ed58c8e2b295a3addf7451b96a55e3c3809 100644 (file)
--- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciIo.h
+++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciIo.h
@@ -25,8 +25,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 EFI_STATUS\r
 InitializePciIoInstance (\r
   PCI_IO_DEVICE  *PciIoDevice\r
-  )\r
-;\r
+  );\r
 \r
 /**\r
   Verifies access to a PCI Base Address Register (BAR)\r
@@ -50,8 +49,7 @@ PciIoVerifyBarAccess (
   IN EFI_PCI_IO_PROTOCOL_WIDTH    Width,\r
   IN UINTN                        Count,\r
   UINT64                          *Offset\r
-  )\r
-;\r
+  );\r
 \r
 /**\r
   Verifies access to a PCI Config Header\r
@@ -71,8 +69,7 @@ PciIoVerifyConfigAccess (
   IN EFI_PCI_IO_PROTOCOL_WIDTH  Width,\r
   IN UINTN                      Count,\r
   IN UINT64                     *Offset\r
-  )\r
-;\r
+  );\r
 \r
 /**\r
   Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is\r
@@ -104,8 +101,7 @@ PciIoPollMem (
   IN  UINT64                     Value,\r
   IN  UINT64                     Delay,\r
   OUT UINT64                     *Result\r
-  )\r
-;\r
+  );\r
 \r
 /**                                                                 \r
   Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is\r
@@ -136,8 +132,7 @@ PciIoPollIo (
   IN  UINT64                     Value,\r
   IN  UINT64                     Delay,\r
   OUT UINT64                     *Result\r
-  )\r
-;\r
+  );\r
 \r
 /**                                                                 \r
   Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
@@ -168,8 +163,7 @@ PciIoMemRead (
   IN     UINT64                     Offset,\r
   IN     UINTN                      Count,\r
   IN OUT VOID                       *Buffer\r
-  )\r
-;\r
+  );\r
 \r
 /**                                                                 \r
   Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
@@ -200,8 +194,7 @@ PciIoMemWrite (
   IN     UINT64                     Offset,\r
   IN     UINTN                      Count,\r
   IN OUT VOID                       *Buffer\r
-  )\r
-;\r
+  );\r
 \r
 /**                                                                 \r
   Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
@@ -232,8 +225,7 @@ PciIoIoRead (
   IN     UINT64                     Offset,\r
   IN     UINTN                      Count,\r
   IN OUT VOID                       *Buffer\r
-  )\r
-;\r
+  );\r
 \r
 /**                                                                 \r
   Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
@@ -264,8 +256,7 @@ PciIoIoWrite (
   IN     UINT64                     Offset,\r
   IN     UINTN                      Count,\r
   IN OUT VOID                       *Buffer\r
-  )\r
-;\r
+  );\r
 \r
 /**                                                                 \r
   Enable a PCI driver to access PCI controller registers in PCI configuration space.\r
@@ -293,8 +284,7 @@ PciIoConfigRead (
   IN     UINT32                     Offset,\r
   IN     UINTN                      Count,\r
   IN OUT VOID                       *Buffer\r
-  )\r
-;\r
+  );\r
 \r
 /**                                                                 \r
   Enable a PCI driver to access PCI controller registers in PCI configuration space.\r
@@ -322,8 +312,7 @@ PciIoConfigWrite (
   IN     UINT32                     Offset,\r
   IN     UINTN                      Count,\r
   IN OUT VOID                       *Buffer\r
-  )\r
-;\r
+  );\r
 \r
 /**                                                                 \r
   Enables a PCI driver to copy one region of PCI memory space to another region of PCI\r
@@ -363,8 +352,7 @@ PciIoCopyMem (
   IN     UINT8                        SrcBarIndex,\r
   IN     UINT64                       SrcOffset,\r
   IN     UINTN                        Count\r
-  )\r
-;\r
+  );\r
 \r
 /**                                                                 \r
   Provides the PCI controller-Cspecific addresses needed to access system memory.\r
@@ -394,8 +382,7 @@ PciIoMap (
   IN OUT UINTN                          *NumberOfBytes,\r
   OUT    EFI_PHYSICAL_ADDRESS           *DeviceAddress,\r
   OUT    VOID                           **Mapping\r
-  )\r
-;\r
+  );\r
 \r
 /**                                                                 \r
   Completes the Map() operation and releases any corresponding resources.\r
@@ -412,8 +399,7 @@ EFIAPI
 PciIoUnmap (\r
   IN  EFI_PCI_IO_PROTOCOL  *This,\r
   IN  VOID                 *Mapping\r
-  )\r
-;\r
+  );\r
 \r
 /**                                                                 \r
   Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer\r
@@ -444,8 +430,7 @@ PciIoAllocateBuffer (
   IN  UINTN                 Pages,\r
   OUT VOID                  **HostAddress,\r
   IN  UINT64                Attributes\r
-  )\r
-;\r
+  );\r
 \r
 /**                                                                 \r
   Frees memory that was allocated with AllocateBuffer().\r
@@ -465,8 +450,7 @@ PciIoFreeBuffer (
   IN  EFI_PCI_IO_PROTOCOL   *This,\r
   IN  UINTN                 Pages,\r
   IN  VOID                  *HostAddress\r
-  )\r
-;\r
+  );\r
 \r
 /**                                                                 \r
   Flushes all PCI posted write transactions from a PCI host bridge to system memory.\r
@@ -483,8 +467,7 @@ EFI_STATUS
 EFIAPI\r
 PciIoFlush (\r
   IN  EFI_PCI_IO_PROTOCOL  *This\r
-  )\r
-;\r
+  );\r
 \r
 /**                                                                 \r
   Retrieves this PCI controller's current PCI bus number, device number, and function number.\r
@@ -507,8 +490,7 @@ PciIoGetLocation (
   OUT UINTN                *Bus,\r
   OUT UINTN                *Device,\r
   OUT UINTN                *Function\r
-  )\r
-;\r
+  );\r
 \r
 /**\r
   Check BAR type for PCI resource.\r
@@ -525,8 +507,7 @@ CheckBarType (
   IN PCI_IO_DEVICE       *PciIoDevice,\r
   UINT8                  BarIndex,\r
   PCI_BAR_TYPE           BarType\r
-  )\r
-;\r
+  );\r
 \r
 /**\r
   Set/Disable new attributes to a Root Bridge\r
@@ -543,8 +524,7 @@ ModifyRootBridgeAttributes (
   IN  PCI_IO_DEVICE                            *PciIoDevice,\r
   IN  UINT64                                   Attributes,\r
   IN  EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION  Operation\r
-  )\r
-;\r
+  );\r
 \r
 /**\r
   Check whether this device can be enable/disable to snoop\r
@@ -559,8 +539,7 @@ EFI_STATUS
 SupportPaletteSnoopAttributes (\r
   IN  PCI_IO_DEVICE                            *PciIoDevice,\r
   IN  EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION  Operation\r
-  )\r
-;\r
+  );\r
 \r
 /**                                                                 \r
   Performs an operation on the attributes that this PCI controller supports. The operations include\r
@@ -588,8 +567,7 @@ PciIoAttributes (
   IN  EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION  Operation,\r
   IN  UINT64                                   Attributes,\r
   OUT UINT64                                   *Result OPTIONAL\r
-  )\r
-;\r
+  );\r
 \r
 /**                                                                 \r
   Gets the attributes that this PCI controller supports setting on a BAR using\r
@@ -620,8 +598,7 @@ PciIoGetBarAttributes (
   IN  UINT8                          BarIndex,\r
   OUT UINT64                         *Supports, OPTIONAL\r
   OUT VOID                           **Resources OPTIONAL\r
-  )\r
-;\r
+  );\r
 \r
 /**                                                                 \r
   Sets the attributes for a range of a BAR on a PCI controller.\r
@@ -655,8 +632,7 @@ PciIoSetBarAttributes (
   IN     UINT8                        BarIndex,\r
   IN OUT UINT64                       *Offset,\r
   IN OUT UINT64                       *Length\r
-  )\r
-;\r
+  );\r
 \r
 /**\r
   Program parent bridge's attribute recurrently.\r
@@ -678,8 +654,7 @@ UpStreamBridgesAttributes (
   IN  PCI_IO_DEVICE                            *PciIoDevice,\r
   IN  EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION  Operation,\r
   IN  UINT64                                   Attributes\r
-  )\r
-;\r
+  );\r
 \r
 /**\r
   Test whether two Pci device has same parent bridge.\r
@@ -693,7 +668,6 @@ BOOLEAN
 PciDevicesOnTheSamePath (\r
   IN PCI_IO_DEVICE        *PciDevice1,\r
   IN PCI_IO_DEVICE        *PciDevice2\r
-  )\r
-;\r
+  );\r
 \r
 #endif\r