\r
Stride = 1 << AccessWidth;\r
AccessAddress += Stride;\r
- if (AccessAddress >= (Address + (1 << Width))) {\r
+ if (AccessAddress >= (Address + LShiftU64 (1ULL, (UINTN)Width))) {\r
//\r
// if all datas have been read, exist\r
//\r
\r
Stride = 1 << AccessWidth;\r
AccessAddress += Stride;\r
- if (AccessAddress >= (Address + (1 << Width))) {\r
+ if (AccessAddress >= (Address + LShiftU64 (1ULL, (UINTN)Width))) {\r
//\r
// if all datas have been written, exist\r
//\r