Patch from open source community for CryptoPkg to allow it to build for ARM using...

[mirror_edk2.git] / IntelFrameworkPkg / FrameworkSpecConformance.txt

diff --git a/IntelFrameworkPkg/FrameworkSpecConformance.txt b/IntelFrameworkPkg/FrameworkSpecConformance.txt
index 96fa3c7c10afa26a156bf5431d3e9c84a321cd1d..5a52bf5190e54af02beb3769dbacccf969d32419 100644 (file)
--- a/IntelFrameworkPkg/FrameworkSpecConformance.txt
+++ b/IntelFrameworkPkg/FrameworkSpecConformance.txt
@@ -864,6 +864,19 @@
     code logic. Therefore developer doesn't need to allocate memory dynamically to construct variable length data record.\r
     Keeping this inconsistency for backward compatibility.\r
 \r
+  21. Guid/DataHubRecords.h\r
+    typedef struct {\r
+      EFI_MISC_COOLING_DEVICE_TYPE      CoolingDeviceType;\r
+      EFI_INTER_LINK_DATA               CoolingDeviceTemperatureLink;\r
+      UINT8                             CoolingDeviceUnitGroup;\r
+      UINT16                            CoolingDeviceNominalSpeed;\r
+      UINT32                            CoolingDeviceOemDefined;\r
+    } EFI_MISC_COOLING_DEVICE_TEMP_LINK_DATA;\r
+\r
+    The "CoolingDeviceUnitGroup" field and "CoolingDeviceNominalSpeed" field are *NOT* consistent with \r
+    MiscSubclass specification 0.9. These fields are aligned with SMBIOS 2.6 specification. And user can easily\r
+    assign any value to CoolingDeviceNominalSpeed.\r
+\r
 ##\r
 # Mismatch with Intel Platform Innovation Framework for Status Codes Specification (Version 0.92)\r
 ##\r
@@ -1193,6 +1206,20 @@
     The enumeration fields listed above are *NOT* defined in Framework SmmCis specification 0.91. EdkII introduces\r
     these fields to support new SMI types.\r
 \r
+  3. Include/Framework/SmmCis.h\r
+    typedef union {\r
+      ///\r
+      /// The processor save-state information for IA-32 processors. \r
+      ///\r
+      EFI_SMI_CPU_SAVE_STATE     Ia32SaveState;\r
+      ///\r
+      /// Note: Inconsistency with the Framework SMM CIS spec - Itanium save state not included.\r
+      ///\r
+      /// The processor save-state information for Itanium processors.\r
+      ///\r
+      /// EFI_PMI_SYSTEM_CONTEXT ItaniumSaveState;\r
+    } EFI_SMM_CPU_SAVE_STATE;\r
+\r
 ##\r
 # Mismatch with Intel Platform Innovation Framework for EFI S3 Resume Boot Path Specification (Version 0.9)\r
 ##\r