The implementation of I/O operation for this library instance \r
are based on EFI_CPU_IO_PROTOCOL.\r
\r
- Copyright (c) 2006, Intel Corporation<BR>\r
- All rights reserved. This program and the accompanying materials\r
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
+\r
+ This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
//\r
// Globle varible to cache pointer to CpuIo protocol.\r
//\r
-EFI_CPU_IO_PROTOCOL *mCpuIo = NULL;\r
-EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo = NULL;\r
+EFI_CPU_IO_PROTOCOL *mCpuIo = NULL;\r
\r
/**\r
The constructor function caches the pointer to CpuIo protocol.\r
IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
- Status = gBS->LocateProtocol (&gEfiPciRootBridgeIoProtocolGuid, NULL, (VOID **) &mPciRootBridgeIo);\r
- if (EFI_ERROR (Status)) {\r
- Status = gBS->LocateProtocol (&gEfiCpuIoProtocolGuid, NULL, (VOID **) &mCpuIo);\r
- }\r
+ Status = gBS->LocateProtocol (&gEfiCpuIoProtocolGuid, NULL, (VOID **) &mCpuIo);\r
ASSERT_EFI_ERROR (Status);\r
\r
return Status;\r
UINT64\r
EFIAPI\r
IoReadWorker (\r
- IN UINTN Port,\r
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width\r
+ IN UINTN Port,\r
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width\r
)\r
{\r
EFI_STATUS Status;\r
UINT64 Data;\r
\r
- if (mPciRootBridgeIo != NULL) {\r
- Status = mPciRootBridgeIo->Io.Read (mPciRootBridgeIo, (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, Port, 1, &Data);\r
- } else {\r
- Status = mCpuIo->Io.Read (mCpuIo, Width, Port, 1, &Data);\r
- }\r
+ Status = mCpuIo->Io.Read (mCpuIo, Width, Port, 1, &Data);\r
ASSERT_EFI_ERROR (Status);\r
\r
return Data;\r
@param Width The width of the I/O operation.\r
@param Data The value to write to the I/O port.\r
\r
- @return The paramter of Data.\r
+ @return The parameter of Data.\r
\r
**/\r
UINT64\r
EFIAPI\r
IoWriteWorker (\r
- IN UINTN Port,\r
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Data\r
+ IN UINTN Port,\r
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Data\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
- if (mPciRootBridgeIo != NULL) {\r
- Status = mPciRootBridgeIo->Io.Write (mPciRootBridgeIo, (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, Port, 1, &Data);\r
- } else {\r
- Status = mCpuIo->Io.Write (mCpuIo, Width, Port, 1, &Data);\r
- }\r
+ Status = mCpuIo->Io.Write (mCpuIo, Width, Port, 1, &Data);\r
ASSERT_EFI_ERROR (Status);\r
\r
return Data;\r
}\r
\r
+/**\r
+ Reads registers in the EFI CPU I/O space.\r
+\r
+ Reads the I/O port specified by Port with registers width specified by Width.\r
+ The port is read Count times, and the read data is stored in the provided Buffer.\r
+\r
+ This function must guarantee that all I/O read and write operations are serialized.\r
+ If such operations are not supported, then ASSERT().\r
+\r
+ @param Port The base address of the I/O operation.\r
+ The caller is responsible for aligning the Address if required.\r
+ @param Width The width of the I/O operation.\r
+ @param Count The number of times to read I/O port.\r
+ @param Buffer The buffer to store the read data into.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+IoReadFifoWorker (\r
+ IN UINTN Port,\r
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ Status = mCpuIo->Io.Read (mCpuIo, Width, Port, Count, Buffer);\r
+ ASSERT_EFI_ERROR (Status);\r
+}\r
+\r
+/**\r
+ Writes registers in the EFI CPU I/O space.\r
+\r
+ Writes the I/O port specified by Port with registers width specified by Width.\r
+ The port is written Count times, and the write data is retrieved from the provided Buffer.\r
+\r
+ This function must guarantee that all I/O read and write operations are serialized.\r
+ If such operations are not supported, then ASSERT().\r
+\r
+ @param Port The base address of the I/O operation.\r
+ The caller is responsible for aligning the Address if required.\r
+ @param Width The width of the I/O operation.\r
+ @param Count The number of times to write I/O port.\r
+ @param Buffer The buffer to store the read data into.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+IoWriteFifoWorker (\r
+ IN UINTN Port,\r
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ Status = mCpuIo->Io.Write (mCpuIo, Width, Port, Count, Buffer);\r
+ ASSERT_EFI_ERROR (Status);\r
+}\r
+\r
/**\r
Reads memory-mapped registers in the EFI system memory space.\r
\r
UINT64\r
EFIAPI\r
MmioReadWorker (\r
- IN UINTN Address,\r
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width\r
+ IN UINTN Address,\r
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT64 Data;\r
+ EFI_STATUS Status;\r
+ UINT64 Data;\r
\r
- if (mPciRootBridgeIo != NULL) {\r
- Status = mPciRootBridgeIo->Mem.Read (mPciRootBridgeIo, (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, Address, 1, &Data);\r
- } else {\r
- Status = mCpuIo->Mem.Read (mCpuIo, Width, Address, 1, &Data);\r
- }\r
+ Status = mCpuIo->Mem.Read (mCpuIo, Width, Address, 1, &Data);\r
ASSERT_EFI_ERROR (Status);\r
\r
return Data;\r
UINT64\r
EFIAPI\r
MmioWriteWorker (\r
- IN UINTN Address,\r
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Data\r
+ IN UINTN Address,\r
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Data\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
- if (mPciRootBridgeIo != NULL) {\r
- Status = mPciRootBridgeIo->Mem.Write (mPciRootBridgeIo, (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, Address, 1, &Data);\r
- } else {\r
- Status = mCpuIo->Mem.Write (mCpuIo, Width, Address, 1, &Data);\r
- }\r
+ Status = mCpuIo->Mem.Write (mCpuIo, Width, Address, 1, &Data);\r
ASSERT_EFI_ERROR (Status);\r
\r
return Data;\r
return IoWriteWorker (Port, EfiCpuIoWidthUint64, Value);\r
}\r
\r
+/**\r
+ Reads an 8-bit I/O port fifo into a block of memory.\r
+\r
+ Reads the 8-bit I/O fifo port specified by Port.\r
+ The port is read Count times, and the read data is\r
+ stored in the provided Buffer.\r
+\r
+ This function must guarantee that all I/O read and write operations are\r
+ serialized.\r
+\r
+ If 8-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to read.\r
+ @param Count The number of times to read I/O port.\r
+ @param Buffer The buffer to store the read data into.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+IoReadFifo8 (\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
+ )\r
+{\r
+ IoReadFifoWorker (Port, EfiCpuIoWidthFifoUint8, Count, Buffer);\r
+}\r
+\r
+/**\r
+ Writes a block of memory into an 8-bit I/O port fifo.\r
+\r
+ Writes the 8-bit I/O fifo port specified by Port.\r
+ The port is written Count times, and the write data is\r
+ retrieved from the provided Buffer.\r
+\r
+ This function must guarantee that all I/O write and write operations are\r
+ serialized.\r
+\r
+ If 8-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param Count The number of times to write I/O port.\r
+ @param Buffer The buffer to retrieve the write data from.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+IoWriteFifo8 (\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
+ )\r
+{\r
+ IoWriteFifoWorker (Port, EfiCpuIoWidthFifoUint8, Count, Buffer);\r
+}\r
+\r
+/**\r
+ Reads a 16-bit I/O port fifo into a block of memory.\r
+\r
+ Reads the 16-bit I/O fifo port specified by Port.\r
+ The port is read Count times, and the read data is\r
+ stored in the provided Buffer.\r
+\r
+ This function must guarantee that all I/O read and write operations are\r
+ serialized.\r
+\r
+ If 16-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to read.\r
+ @param Count The number of times to read I/O port.\r
+ @param Buffer The buffer to store the read data into.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+IoReadFifo16 (\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
+ )\r
+{\r
+ //\r
+ // Make sure Port is aligned on a 16-bit boundary.\r
+ //\r
+ ASSERT ((Port & 1) == 0);\r
+ IoReadFifoWorker (Port, EfiCpuIoWidthFifoUint16, Count, Buffer);\r
+}\r
+\r
+/**\r
+ Writes a block of memory into a 16-bit I/O port fifo.\r
+\r
+ Writes the 16-bit I/O fifo port specified by Port.\r
+ The port is written Count times, and the write data is\r
+ retrieved from the provided Buffer.\r
+\r
+ This function must guarantee that all I/O write and write operations are\r
+ serialized.\r
+\r
+ If 16-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param Count The number of times to write I/O port.\r
+ @param Buffer The buffer to retrieve the write data from.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+IoWriteFifo16 (\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
+ )\r
+{\r
+ //\r
+ // Make sure Port is aligned on a 16-bit boundary.\r
+ //\r
+ ASSERT ((Port & 1) == 0);\r
+ IoWriteFifoWorker (Port, EfiCpuIoWidthFifoUint16, Count, Buffer);\r
+}\r
+\r
+/**\r
+ Reads a 32-bit I/O port fifo into a block of memory.\r
+\r
+ Reads the 32-bit I/O fifo port specified by Port.\r
+ The port is read Count times, and the read data is\r
+ stored in the provided Buffer.\r
+\r
+ This function must guarantee that all I/O read and write operations are\r
+ serialized.\r
+\r
+ If 32-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to read.\r
+ @param Count The number of times to read I/O port.\r
+ @param Buffer The buffer to store the read data into.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+IoReadFifo32 (\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
+ )\r
+{\r
+ //\r
+ // Make sure Port is aligned on a 32-bit boundary.\r
+ //\r
+ ASSERT ((Port & 3) == 0);\r
+ IoReadFifoWorker (Port, EfiCpuIoWidthFifoUint32, Count, Buffer);\r
+}\r
+\r
+/**\r
+ Writes a block of memory into a 32-bit I/O port fifo.\r
+\r
+ Writes the 32-bit I/O fifo port specified by Port.\r
+ The port is written Count times, and the write data is\r
+ retrieved from the provided Buffer.\r
+\r
+ This function must guarantee that all I/O write and write operations are\r
+ serialized.\r
+\r
+ If 32-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param Count The number of times to write I/O port.\r
+ @param Buffer The buffer to retrieve the write data from.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+IoWriteFifo32 (\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
+ )\r
+{\r
+ //\r
+ // Make sure Port is aligned on a 32-bit boundary.\r
+ //\r
+ ASSERT ((Port & 3) == 0);\r
+ IoWriteFifoWorker (Port, EfiCpuIoWidthFifoUint32, Count, Buffer);\r
+}\r
+\r
/**\r
Reads an 8-bit MMIO register.\r
\r
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