IntelFsp2WrapperPkg: Support FSP Dispatch mode

[mirror_edk2.git] / IntelFsp2WrapperPkg / IntelFsp2WrapperPkg.dec

diff --git a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec b/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
index b76e611150ecad0e0488168be327366a8e17d4ed..b901562bb3ef6be4e3b792d9eb5751779e9154af 100644 (file)
--- a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+++ b/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
@@ -1,7 +1,7 @@
 ## @file\r
 # Provides drivers and definitions to support fsp in EDKII bios.\r
 #\r
-# Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>\r
 # This program and the accompanying materials are licensed and made available under\r
 # the terms and conditions of the BSD License that accompanies this distribution.\r
 # The full text of the license may be found at\r
@@ -36,7 +36,7 @@
   #\r
   # GUID defined in package\r
   #\r
-  gFspWrapperTokenSpaceGuid             = { 0xa34cf082, 0xf50, 0x4f0d,  { 0x89, 0x8a, 0x3d, 0x39, 0x30, 0x2b, 0xc5, 0x1e } }\r
+  gIntelFsp2WrapperTokenSpaceGuid       = { 0xa34cf082, 0xf50, 0x4f0d,  { 0x89, 0x8a, 0x3d, 0x39, 0x30, 0x2b, 0xc5, 0x1e } }\r
   gFspApiPerformanceGuid                = { 0xc9122295, 0x56ed, 0x4d4e, { 0x06, 0xa6, 0x50, 0x8d, 0x89, 0x4d, 0x3e, 0x40 } }\r
   gFspHobGuid                           = { 0x6d86fb36, 0xba90, 0x472c, { 0xb5, 0x83, 0x3f, 0xbe, 0xd3, 0xfb, 0x20, 0x9a } }\r
 \r
@@ -56,22 +56,61 @@
 ################################################################################\r
 [PcdsFixedAtBuild, PcdsPatchableInModule]\r
   ## Provides the memory mapped base address of the BIOS CodeCache Flash Device.\r
-  gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFFE00000|UINT32|0x10000001\r
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFFE00000|UINT32|0x10000001\r
   ## Provides the size of the BIOS Flash Device.\r
-  gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize|0x00200000|UINT32|0x10000002\r
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize|0x00200000|UINT32|0x10000002\r
 \r
   ## Indicates the base address of the first Microcode Patch in the Microcode Region\r
-  gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x10000005\r
-  gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x10000006\r
+  gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x10000005\r
+  gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x10000006\r
   ## Indicates the offset of the Cpu Microcode.\r
-  gFspWrapperTokenSpaceGuid.PcdFlashMicrocodeOffset|0x90|UINT32|0x10000007\r
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset|0x90|UINT32|0x10000007\r
 \r
   ## Indicate the PEI memory size platform want to report\r
-  gFspWrapperTokenSpaceGuid.PcdPeiMinMemSize|0x1800000|UINT32|0x40000004\r
+  gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x1800000|UINT32|0x40000004\r
   ## Indicate the PEI memory size platform want to report\r
-  gFspWrapperTokenSpaceGuid.PcdPeiRecoveryMinMemSize|0x3000000|UINT32|0x40000005\r
+  gIntelFsp2WrapperTokenSpaceGuid.PcdPeiRecoveryMinMemSize|0x3000000|UINT32|0x40000005\r
 \r
-  ## This is the base address of FSP-T/M/S\r
-  gFspWrapperTokenSpaceGuid.PcdFsptBaseAddress|0x00000000|UINT32|0x00000300\r
-  gFspWrapperTokenSpaceGuid.PcdFspmBaseAddress|0x00000000|UINT32|0x00000301\r
-  gFspWrapperTokenSpaceGuid.PcdFspsBaseAddress|0x00000000|UINT32|0x00000302\r
+  ## This is the base address of FSP-T
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0x00000000|UINT32|0x00000300\r
+\r
+  ## This PCD indicates if FSP APIs are skipped from FSP wrapper.<BR><BR>\r
+  #  If a bit is set, that means this FSP API is skipped.<BR>\r
+  #  If a bit is clear, that means this FSP API is NOT skipped.<BR>\r
+  #  NOTE: Only NotifyPhase Post PCI enumeration (BIT16) is implemented.<BR>\r
+  #  BIT[15:0] is for function:<BR>\r
+  #    BIT0    - Skip TempRamInit<BR>\r
+  #    BIT1    - Skip MemoryInit<BR>\r
+  #    BIT2    - Skip TempRamExit<BR>\r
+  #    BIT3    - Skip SiliconInit<BR>\r
+  #    BIT4    - Skip NotifyPhase<BR>\r
+  #  BIT[32:16] is for sub-function:<BR>\r
+  #    BIT16   - Skip NotifyPhase (AfterPciEnumeration)<BR>\r
+  #    BIT17   - Skip NotifyPhase (ReadyToBoot)<BR>\r
+  #    BIT18   - Skip NotifyPhase (EndOfFirmware)<BR>\r
+  #  Any undefined BITs are reserved for future use.<BR>\r
+  # @Prompt Skip FSP API from FSP wrapper.\r
+  gIntelFsp2WrapperTokenSpaceGuid.PcdSkipFspApi|0x00000000|UINT32|0x40000009\r
+\r
+  ## This PCD decides how Wrapper code utilizes FSP
+  # 0: DISPATCH mode (FSP Wrapper will load PeiCore from FSP without calling FSP API)
+  # 1: API mode (FSP Wrapper will call FSP API)
+  #
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0x00000001|UINT8|0x4000000A
+
+[PcdsFixedAtBuild, PcdsPatchableInModule,PcdsDynamic,PcdsDynamicEx]\r
+  #
+  ## These are the base address of FSP-M/S
+  #
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0x00000000|UINT32|0x00001000
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0x00000000|UINT32|0x00001001\r
+  #\r
+  # To provide flexibility for platform to pre-allocate FSP UPD buffer\r
+  #\r
+  # The PCDs define the pre-allocated FSPM and FSPS UPD Data Buffer Address.\r
+  # 0x00000000 - Platform will not pre-allocate UPD buffer before FspWrapper module\r
+  # non-zero   - Platform will pre-allocate UPD buffer and patch this value to\r
+  #              buffer address before FspWrapper module executing.\r
+  #\r
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x00000000|UINT32|0x50000000\r
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0x00000000|UINT32|0x50000001\r