Add IntelFsp2Pkg and IntelFsp2WrapperPkg.

[mirror_edk2.git] / IntelFsp2WrapperPkg / Library / SecFspWrapperPlatformSecLibSample / Ia32 / PeiCoreEntry.S

diff --git a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/PeiCoreEntry.S b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/PeiCoreEntry.S
new file mode 100644 (file)
index 0000000..c35f02b
--- /dev/null
+++ b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/PeiCoreEntry.S
@@ -0,0 +1,130 @@
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution.  The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+# Module Name:\r
+#\r
+#  PeiCoreEntry.S\r
+#\r
+# Abstract:\r
+#\r
+#   Find and call SecStartup\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+ASM_GLOBAL ASM_PFX(CallPeiCoreEntryPoint)\r
+ASM_PFX(CallPeiCoreEntryPoint):\r
+  #\r
+  # Obtain the hob list pointer\r
+  #\r
+  movl    0x4(%esp), %eax\r
+  #\r
+  # Obtain the stack information\r
+  #   ECX: start of range\r
+  #   EDX: end of range\r
+  #\r
+  movl    0x8(%esp), %ecx\r
+  movl    0xC(%esp), %edx\r
+\r
+  #\r
+  # Platform init\r
+  #\r
+  pushal\r
+  pushl %edx\r
+  pushl %ecx\r
+  pushl %eax\r
+  call  ASM_PFX(PlatformInit)\r
+  popl  %eax\r
+  popl  %eax\r
+  popl  %eax\r
+  popal\r
+\r
+  #\r
+  # Set stack top pointer\r
+  #\r
+  movl    %edx, %esp\r
+\r
+  #\r
+  # Push the hob list pointer\r
+  #\r
+  pushl   %eax\r
+\r
+  #\r
+  # Save the value\r
+  #   ECX: start of range\r
+  #   EDX: end of range\r
+  #\r
+  movl    %esp, %ebp\r
+  pushl   %ecx\r
+  pushl   %edx\r
+\r
+  #\r
+  # Push processor count to stack first, then BIST status (AP then BSP)\r
+  #\r
+  movl    $1, %eax\r
+  cpuid\r
+  shr     $16, %ebx\r
+  andl    $0x000000FF, %ebx\r
+  cmp     $1, %bl\r
+  jae     PushProcessorCount\r
+\r
+  #\r
+  # Some processors report 0 logical processors.  Effectively 0 = 1.\r
+  # So we fix up the processor count\r
+  #\r
+  inc     %ebx\r
+\r
+PushProcessorCount:\r
+  pushl   %ebx\r
+\r
+  #\r
+  # We need to implement a long-term solution for BIST capture.  For now, we just copy BSP BIST\r
+  # for all processor threads\r
+  #\r
+  xorl    %ecx, %ecx\r
+  movb    %bl, %cl\r
+PushBist:\r
+  movd    %mm0, %eax\r
+  pushl   %eax\r
+  loop    PushBist\r
+\r
+  # Save Time-Stamp Counter\r
+  movd  %mm5, %eax\r
+  pushl %eax\r
+\r
+  movd  %mm6, %eax\r
+  pushl %eax\r
+\r
+  #\r
+  # Pass entry point of the PEI core\r
+  #\r
+  movl    $0xFFFFFFE0, %edi\r
+  pushl   %ds:(%edi)\r
+\r
+  #\r
+  # Pass BFV into the PEI Core\r
+  #\r
+  movl    $0xFFFFFFFC, %edi\r
+  pushl   %ds:(%edi)\r
+\r
+  #\r
+  # Pass stack size into the PEI Core\r
+  #\r
+  movl    -4(%ebp), %ecx\r
+  movl    -8(%ebp), %edx\r
+  pushl   %ecx       # RamBase\r
+\r
+  subl    %ecx, %edx\r
+  pushl   %edx       # RamSize\r
+\r
+  #\r
+  # Pass Control into the PEI Core\r
+  #\r
+  call ASM_PFX(SecStartup)\r