Add IntelFsp2Pkg and IntelFsp2WrapperPkg.

[mirror_edk2.git] / IntelFsp2WrapperPkg / Library / SecFspWrapperPlatformSecLibSample / Ia32 / PeiCoreEntry.asm

diff --git a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/PeiCoreEntry.asm b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/PeiCoreEntry.asm
new file mode 100644 (file)
index 0000000..cd1c7b8
--- /dev/null
+++ b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/PeiCoreEntry.asm
@@ -0,0 +1,140 @@
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution.  The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+;  PeiCoreEntry.asm\r
+;\r
+; Abstract:\r
+;\r
+;   Find and call SecStartup\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+.686p\r
+.xmm\r
+.model flat, c\r
+.code\r
+\r
+EXTRN   SecStartup:NEAR\r
+EXTRN   PlatformInit:NEAR\r
+\r
+CallPeiCoreEntryPoint   PROC PUBLIC\r
+  ;\r
+  ; Obtain the hob list pointer\r
+  ;\r
+  mov     eax, [esp+4]\r
+  ;\r
+  ; Obtain the stack information\r
+  ;   ECX: start of range\r
+  ;   EDX: end of range\r
+  ;\r
+  mov     ecx, [esp+8]\r
+  mov     edx, [esp+0Ch]\r
+\r
+  ;\r
+  ; Platform init\r
+  ;\r
+  pushad\r
+  push edx\r
+  push ecx\r
+  push eax\r
+  call PlatformInit\r
+  pop  eax\r
+  pop  eax\r
+  pop  eax\r
+  popad\r
+\r
+  ;\r
+  ; Set stack top pointer\r
+  ;\r
+  mov     esp, edx\r
+\r
+  ;\r
+  ; Push the hob list pointer\r
+  ;\r
+  push    eax\r
+\r
+  ;\r
+  ; Save the value\r
+  ;   ECX: start of range\r
+  ;   EDX: end of range\r
+  ;\r
+  mov     ebp, esp\r
+  push    ecx\r
+  push    edx\r
+\r
+  ;\r
+  ; Push processor count to stack first, then BIST status (AP then BSP)\r
+  ;\r
+  mov     eax, 1\r
+  cpuid\r
+  shr     ebx, 16\r
+  and     ebx, 0000000FFh\r
+  cmp     bl, 1\r
+  jae     PushProcessorCount\r
+\r
+  ;\r
+  ; Some processors report 0 logical processors.  Effectively 0 = 1.\r
+  ; So we fix up the processor count\r
+  ;\r
+  inc     ebx\r
+\r
+PushProcessorCount:\r
+  push    ebx\r
+\r
+  ;\r
+  ; We need to implement a long-term solution for BIST capture.  For now, we just copy BSP BIST\r
+  ; for all processor threads\r
+  ;\r
+  xor     ecx, ecx\r
+  mov     cl, bl\r
+PushBist:\r
+  movd    eax, mm0\r
+  push    eax\r
+  loop    PushBist\r
+\r
+  ; Save Time-Stamp Counter\r
+  movd eax, mm5\r
+  push eax\r
+\r
+  movd eax, mm6\r
+  push eax\r
+\r
+  ;\r
+  ; Pass entry point of the PEI core\r
+  ;\r
+  mov     edi, 0FFFFFFE0h\r
+  push    DWORD PTR ds:[edi]\r
+\r
+  ;\r
+  ; Pass BFV into the PEI Core\r
+  ;\r
+  mov     edi, 0FFFFFFFCh\r
+  push    DWORD PTR ds:[edi]\r
+\r
+  ;\r
+  ; Pass stack size into the PEI Core\r
+  ;\r
+  mov     ecx, [ebp - 4]\r
+  mov     edx, [ebp - 8]\r
+  push    ecx       ; RamBase\r
+\r
+  sub     edx, ecx\r
+  push    edx       ; RamSize\r
+\r
+  ;\r
+  ; Pass Control into the PEI Core\r
+  ;\r
+  call SecStartup\r
+CallPeiCoreEntryPoint   ENDP\r
+\r
+END\r