#------------------------------------------------------------------------------\r
#\r
-# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution. The full text of the license may be found at\r
#\r
# Following functions will be provided in C\r
#\r
-ASM_GLOBAL ASM_PFX(FspImageSizeOffset)\r
ASM_GLOBAL ASM_PFX(SecStartup)\r
ASM_GLOBAL ASM_PFX(FspApiCallingCheck)\r
\r
#\r
# Save return address to EBP\r
#\r
- movl %eax, %ebp\r
+ movd %xmm7, %ebp\r
+\r
cmpl $0x00, %esp\r
jz ParamError\r
movl (%esp), %eax #dword ptr [] Parameter pointer\r
jmp *%ebp\r
\r
\r
+#----------------------------------------------------------------------------\r
+# EstablishStackFsp\r
+#\r
+# Following is the code copied from BYTFSP, need to figure out what it is doing..\r
+#\r
+#----------------------------------------------------------------------------\r
+ASM_GLOBAL ASM_PFX(EstablishStackFsp)\r
+ASM_PFX(EstablishStackFsp):\r
+ #\r
+ # Save parameter pointer in edx \r
+ #\r
+ movl 4(%esp), %edx\r
+ \r
+ #\r
+ # Enable FSP STACK\r
+ #\r
+ movl PcdGet32(PcdTemporaryRamBase), %esp\r
+ addl PcdGet32(PcdTemporaryRamSize), %esp\r
+\r
+ pushl $DATA_LEN_OF_MCUD # Size of the data region\r
+ pushl $0x4455434D # Signature of the data region 'MCUD'\r
+ pushl 12(%edx) # Code size\r
+ pushl 8(%edx) # Code base\r
+ cmpl $0, %edx # Is parameter pointer valid ?\r
+ jz InvalidMicrocodeRegion\r
+ pushl 4(%edx) # Microcode size\r
+ pushl (%edx) # Microcode base\r
+ jmp EstablishStackFspExit\r
+\r
+InvalidMicrocodeRegion:\r
+ push $0 # Microcode size\r
+ push $0 # Microcode base\r
+ \r
+EstablishStackFspExit:\r
+ #\r
+ # Save API entry/exit timestamp into stack\r
+ #\r
+ pushl $DATA_LEN_OF_PER0 # Size of the data region\r
+ pushl $0x30524550 # Signature of the data region 'PER0'\r
+ movd %xmm4, %eax\r
+ pushl %eax\r
+ movd %xmm5, %eax\r
+ pushl %eax\r
+ rdtsc\r
+ pushl %edx\r
+ pushl %eax\r
+\r
+ #\r
+ # Terminator for the data on stack\r
+ # \r
+ push $0x00\r
+\r
+ #\r
+ # Set ECX/EDX to the bootloader temporary memory range\r
+ #\r
+ movl PcdGet32 (PcdTemporaryRamBase), %ecx\r
+ movl %ecx, %edx\r
+ addl PcdGet32 (PcdTemporaryRamSize), %edx\r
+ subl PcdGet32 (PcdFspTemporaryRamSize), %edx\r
+\r
+ xorl %eax, %eax\r
+ \r
+ movd %mm7, %esi #RET_ESI\r
+ jmp *%esi\r
+\r
#----------------------------------------------------------------------------\r
# TempRamInit API\r
#\r
# Save timestamp into XMM4 & XMM5\r
#\r
rdtsc\r
- SAVE_EAX\r
- SAVE_EDX\r
-\r
- #\r
- # Check Parameter\r
- #\r
- movl 4(%esp), %eax\r
- cmpl $0x00, %eax\r
- movl $0x80000002, %eax\r
- jz NemInitExit\r
+ movd %edx, %xmm4\r
+ movd %eax, %xmm5\r
\r
#\r
# CPUID/DeviceID check\r
#\r
movl $TempRamInitApiL0, %eax\r
- jmp ASM_PFX(FspSelfCheckDflt) # Note: ESP can not be changed.\r
+ jmp ASM_PFX(FspSelfCheckDflt) # @note: ESP can not be changed.\r
TempRamInitApiL0:\r
cmpl $0x00, %eax\r
jnz NemInitExit\r
\r
#\r
- # Platform Basic Init.\r
+ # Sec Platform Init\r
#\r
- movl $TempRamInitApiL1, %eax\r
- jmp ASM_PFX(PlatformBasicInitDflt)\r
+ movl $TempRamInitApiL1, %esi #CALL_MMX SecPlatformInit\r
+ movd %mm7, %esi\r
+ jmp ASM_PFX(SecPlatformInit)\r
TempRamInitApiL1:\r
- cmpl $0x00, %eax\r
- jnz NemInitExit\r
\r
#\r
- # Load microcode\r
+ # Call Sec CAR Init\r
#\r
- movl $TempRamInitApiL2, %eax\r
- addl $0x04, %esp\r
- jmp LoadUcode\r
-\r
+ movl $TempRamInitApiL2, %esi #CALL_MMX SecCarInit\r
+ movd %mm7, %esi\r
+ jmp ASM_PFX(SecCarInit)\r
TempRamInitApiL2:\r
- LOAD_ESP\r
- cmpl $0x00, %eax\r
- jnz NemInitExit\r
-\r
- #\r
- # Call platform NEM init\r
- #\r
- movl $TempRamInitApiL3, %eax\r
- addl $0x04, %esp\r
- jmp ASM_PFX(PlatformTempRamInit)\r
-TempRamInitApiL3:\r
- subl $0x04, %esp\r
- cmpl $0x00, %eax\r
- jnz NemInitExit\r
-\r
- #\r
- # Save parameter pointer in edx\r
- #\r
- movl 4(%esp), %edx\r
-\r
- #\r
- # Enable FSP STACK\r
- #\r
- movl ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamBase), %esp\r
- addl ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamSize), %esp\r
\r
- pushl $DATA_LEN_OF_MCUD # Size of the data region\r
- pushl $0x4455434D # Signature of the data region 'MCUD'\r
- pushl 4(%edx) # Microcode size\r
- pushl (%edx) # Microcode base\r
- pushl 12(%edx) # Code size\r
- pushl 8(%edx) # Code base\r
+ # @todo: ESP has been modified, we need to restore here.\r
\r
- #\r
- # Save API entry/exit timestamp into stack\r
- #\r
- pushl $DATA_LEN_OF_PER0 # Size of the data region\r
- pushl $0x30524550 # Signature of the data region 'PER0'\r
- rdtsc\r
- pushl %edx\r
- pushl %eax\r
- LOAD_EAX\r
- LOAD_EDX\r
- pushl %edx\r
- pushl %eax\r
+ LOAD_REGS\r
+ SAVE_REGS\r
\r
#\r
- # Terminator for the data on stack\r
+ # Load microcode\r
#\r
- pushl $0x00\r
+ movl $TempRamInitApiL3, %esi #CALL_MMX LoadUcode\r
+ movd %mm7, %esi\r
+ jmp ASM_PFX(LoadUcode)\r
+TempRamInitApiL3:\r
\r
#\r
- # Set ECX/EDX to the bootloader temporary memory range\r
+ # EstablishStackFsp\r
#\r
- movl ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamBase), %ecx\r
- movl %ecx, %edx\r
- addl ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamSize), %edx\r
- subl ASM_PFX(_gPcd_FixedAtBuild_PcdFspTemporaryRamSize), %edx\r
-\r
- xorl %eax, %eax\r
+ movl $TempRamInitApiL4, %esi #CALL_MMX EstablishStackFsp\r
+ movd %mm7, %esi\r
+ jmp ASM_PFX(EstablishStackFsp)\r
+TempRamInitApiL4:\r
\r
NemInitExit:\r
#\r
LOAD_REGS\r
ret\r
\r
-\r
#----------------------------------------------------------------------------\r
# FspInit API\r
#\r
#----------------------------------------------------------------------------\r
ASM_GLOBAL ASM_PFX(FspInitApi)\r
ASM_PFX(FspInitApi):\r
+ movl $0x01, %eax\r
+ jmp FspApiCommon\r
+\r
+#----------------------------------------------------------------------------\r
+# NotifyPhase API\r
+#\r
+# This FSP API will notify the FSP about the different phases in the boot\r
+# process\r
+#\r
+#----------------------------------------------------------------------------\r
+ASM_GLOBAL ASM_PFX(NotifyPhaseApi)\r
+ASM_PFX(NotifyPhaseApi):\r
+ movl $0x02, %eax\r
+ jmp FspApiCommon\r
+\r
+#----------------------------------------------------------------------------\r
+# FspMemoryInit API\r
+#\r
+# This FSP API is called after TempRamInit and initializes the memory.\r
+#\r
+#----------------------------------------------------------------------------\r
+ASM_GLOBAL ASM_PFX(FspMemoryInitApi)\r
+ASM_PFX(FspMemoryInitApi):\r
+ movl $0x03, %eax\r
+ jmp FspApiCommon\r
+\r
+#----------------------------------------------------------------------------\r
+# TempRamExitApi API\r
+#\r
+# This API tears down temporary RAM\r
+#\r
+#----------------------------------------------------------------------------\r
+ASM_GLOBAL ASM_PFX(TempRamExitApi)\r
+ASM_PFX(TempRamExitApi):\r
+ movl $0x04, %eax\r
+ jmp FspApiCommon\r
+\r
+#----------------------------------------------------------------------------\r
+# FspSiliconInit API\r
+#\r
+# This FSP API initializes the CPU and the chipset including the IO\r
+# controllers in the chipset to enable normal operation of these devices.\r
+#\r
+#----------------------------------------------------------------------------\r
+ASM_GLOBAL ASM_PFX(FspSiliconInitApi)\r
+ASM_PFX(FspSiliconInitApi):\r
+ movl $0x05, %eax\r
+ jmp FspApiCommon\r
+\r
+#----------------------------------------------------------------------------\r
+# FspApiCommon API\r
+#\r
+# This is the FSP API common entry point to resume the FSP execution\r
+#\r
+#----------------------------------------------------------------------------\r
+ASM_GLOBAL ASM_PFX(FspApiCommon)\r
+ASM_PFX(FspApiCommon):\r
#\r
- # Stack must be ready\r
+ # EAX holds the API index\r
#\r
- pushl $0x087654321\r
- popl %eax\r
- cmpl $0x087654321, %eax\r
- jz FspInitApiL0\r
+\r
+ #\r
+ # Stack must be ready\r
+ # \r
+ pushl %eax\r
+ addl $0x04, %esp\r
+ cmpl -4(%esp), %eax\r
+ jz FspApiCommonL0\r
movl $0x080000003, %eax\r
- jmp FspInitApiexit\r
+ jmp FspApiCommonExit\r
\r
-FspInitApiL0:\r
+FspApiCommonL0:\r
#\r
- # Additional check\r
+ # Verify the calling condition\r
#\r
- pusha\r
- pushl $0x01\r
+ pushal\r
+ pushl %eax\r
call ASM_PFX(FspApiCallingCheck)\r
addl $0x04, %esp\r
- movl %eax, 28(%esp)\r
- popa\r
cmpl $0x00, %eax\r
- jz FspInitApiL1\r
- jmp FspInitApiexit\r
+ jz FspApiCommonL1\r
+ movl %eax, 0x1C(%esp) # mov dword ptr [esp + 4 * 7], eax\r
+ popal\r
+ ret\r
+\r
+FspApiCommonL1:\r
+ popal\r
+ cmpl $0x01, %eax # FspInit API\r
+ jz FspApiCommonL2\r
+ cmpl $0x03, %eax # FspMemoryInit API\r
+ jz FspApiCommonL2\r
+ jmp Pei2LoaderSwitchStack\r
\r
-FspInitApiL1:\r
+FspApiCommonL2:\r
+ #\r
+ # FspInit and FspMemoryInit APIs, setup the initial stack frame\r
+ # \r
+ \r
#\r
# Store the address in FSP which will return control to the BL\r
#\r
- pushl $FspInitApiexit\r
+ pushl $FspApiCommonExit\r
\r
#\r
# Create a Task Frame in the stack for the Boot Loader\r
#\r
- pushfl # 2 pushf for 4 byte alignment\r
+ pushfl # 2 pushf for 4 byte alignment\r
cli\r
pushal\r
\r
#\r
# Setup new FSP stack\r
#\r
- movl %esp, %eax\r
- movl ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamBase), %esp\r
- addl ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamSize), %esp\r
+ movl %esp, %edi\r
+ movl PcdGet32(PcdTemporaryRamBase), %esp\r
+ addl PcdGet32(PcdTemporaryRamSize), %esp\r
subl $(DATA_LEN_AT_STACK_TOP + 0x40), %esp\r
\r
- # Save the bootloader's stack pointer\r
#\r
- pushl %eax\r
+ # Pass the API Idx to SecStartup\r
+ #\r
+ pushl %eax\r
+ \r
+ #\r
+ # Pass the bootloader stack to SecStartup\r
+ #\r
+ pushl %edi\r
\r
#\r
# Pass entry point of the PEI core\r
#\r
- call ASM_PFX(GetFspBaseAddress)\r
- movl ASM_PFX(FspImageSizeOffset), %edi\r
- movl (%eax, %edi), %edi\r
- addl %eax, %edi\r
- subl $0x20, %edi\r
- addl (%edi), %eax\r
- pushl %eax\r
+ call ASM_PFX(GetFspBaseAddress)\r
+ movl %eax, %edi\r
+ addl PcdGet32(PcdFspAreaSize), %edi\r
+ subl $0x20, %edi\r
+ addl %ds:(%edi), %eax\r
+ pushl %eax\r
\r
#\r
# Pass BFV into the PEI Core\r
# PcdFspAreaBaseAddress are the same. For FSP with mulitple FVs,\r
# they are different. The code below can handle both cases.\r
#\r
- call ASM_PFX(GetFspBaseAddress)\r
- movl %eax , %edi\r
- call ASM_PFX(GetBootFirmwareVolumeOffset)\r
- addl %edi ,%eax\r
- pushl %eax\r
+ call ASM_PFX(GetFspBaseAddress)\r
+ movl %eax, %edi\r
+ call ASM_PFX(GetBootFirmwareVolumeOffset)\r
+ addl %edi, %eax\r
+ pushl %eax\r
\r
#\r
# Pass stack base and size into the PEI Core\r
#\r
- movl ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamBase), %eax\r
- addl ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamSize), %eax\r
- subl ASM_PFX(_gPcd_FixedAtBuild_PcdFspTemporaryRamSize), %eax\r
- pushl %eax\r
- pushl ASM_PFX(_gPcd_FixedAtBuild_PcdFspTemporaryRamSize)\r
+ movl PcdGet32(PcdTemporaryRamBase), %eax\r
+ addl PcdGet32(PcdTemporaryRamSize), %eax\r
+ subl PcdGet32(PcdFspTemporaryRamSize), %eax\r
+ pushl %eax\r
+ pushl PcdGet32(PcdFspTemporaryRamSize)\r
\r
#\r
# Pass Control into the PEI Core\r
#\r
call ASM_PFX(SecStartup)\r
\r
-FspInitApiexit:\r
- ret\r
-\r
-\r
-#----------------------------------------------------------------------------\r
-# NotifyPhase API\r
-#\r
-# This FSP API will notify the FSP about the different phases in the boot\r
-# process\r
-#\r
-#----------------------------------------------------------------------------\r
-ASM_GLOBAL ASM_PFX(NotifyPhaseApi)\r
-ASM_PFX(NotifyPhaseApi):\r
- #\r
- # Stack must be ready\r
- #\r
- pushl $0x0087654321\r
- popl %eax\r
- cmpl $0x087654321, %eax\r
- jz NotifyPhaseApiL0\r
- movl $0x080000003, %eax\r
- jmp NotifyPhaseApiErrExit\r
-\r
-NotifyPhaseApiL0:\r
- #\r
- # Verify the calling condition\r
- #\r
- pusha\r
- pushl $0x02\r
- call ASM_PFX(FspApiCallingCheck)\r
- addl $0x04, %esp\r
- movl %eax, 28(%esp)\r
- popa\r
-\r
- cmpl $0x00, %eax\r
- jz NotifyPhaseApiL1\r
-\r
- #\r
- # Error return\r
- #\r
-NotifyPhaseApiErrExit:\r
+FspApiCommonExit:\r
ret\r
\r
-NotifyPhaseApiL1:\r
- jmp ASM_PFX(Pei2LoaderSwitchStack)\r
-\r
-\r
\r
-#END\r
projects / mirror_edk2.git / blobdiff