Update IntelFspPkg according to FSP1.1.

[mirror_edk2.git] / IntelFspPkg / Include / FspInfoHeader.h

diff --git a/IntelFspPkg/Include/FspInfoHeader.h b/IntelFspPkg/Include/FspInfoHeader.h
index cde7b599c9192797989fcbab16fbfb04b986ef73..3033659ea01e5c07f936ed229c36dd10abe046f8 100644 (file)
--- a/IntelFspPkg/Include/FspInfoHeader.h
+++ b/IntelFspPkg/Include/FspInfoHeader.h
@@ -2,7 +2,7 @@
   Intel FSP Info Header definition from Intel Firmware Support Package External\r
   Architecture Specification, April 2014, revision 001.\r
 \r
-  Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -16,6 +16,12 @@
 #ifndef _FSP_INFO_HEADER_H_\r
 #define _FSP_INFO_HEADER_H_\r
 \r
+#define FSP_HEADER_REVISION_1   1\r
+#define FSP_HEADER_REVISION_2   2\r
+\r
+#define FSPE_HEADER_REVISION_1  1\r
+#define FSPP_HEADER_REVISION_1  1\r
+\r
 ///\r
 /// Fixed FSP header offset in the FSP image\r
 ///\r
@@ -27,79 +33,125 @@
 \r
 typedef struct  {\r
   ///\r
-  /// Signature ('FSPH') for the FSP Information Header\r
+  /// Byte 0x00: Signature ('FSPH') for the FSP Information Header\r
   ///\r
   UINT32  Signature;\r
   ///\r
-  /// Length of the FSP Information Header\r
+  /// Byte 0x04: Length of the FSP Information Header\r
   ///\r
   UINT32  HeaderLength;\r
   ///\r
-  /// Reserved\r
+  /// Byte 0x08: Reserved\r
   ///\r
   UINT8   Reserved1[3];\r
   ///\r
-  /// Revision of the FSP Information Header\r
+  /// Byte 0x0B: Revision of the FSP Information Header\r
   ///\r
   UINT8   HeaderRevision;\r
   ///\r
-  /// Revision of the FSP binary\r
+  /// Byte 0x0C: Revision of the FSP binary\r
   ///\r
   UINT32  ImageRevision;\r
 \r
 \r
   ///\r
-  /// Signature string that will help match the FSP Binary to a supported\r
+  /// Byte 0x10: Signature string that will help match the FSP Binary to a supported\r
   /// hardware configuration.\r
   ///\r
   CHAR8   ImageId[8];\r
   ///\r
-  /// Size of the entire FSP binary\r
+  /// Byte 0x18: Size of the entire FSP binary\r
   ///\r
   UINT32  ImageSize;\r
   ///\r
-  /// FSP binary preferred base address\r
+  /// Byte 0x18: FSP binary preferred base address\r
   ///\r
   UINT32  ImageBase;\r
 \r
 \r
   ///\r
-  /// Attribute for the FSP binary\r
+  /// Byte 0x20: Attribute for the FSP binary\r
   ///\r
   UINT32  ImageAttribute;\r
   ///\r
-  /// Offset of the FSP configuration region\r
+  /// Byte 0x24: Offset of the FSP configuration region\r
   ///\r
   UINT32  CfgRegionOffset;\r
   ///\r
-  /// Size of the FSP configuration region\r
+  /// Byte 0x24: Size of the FSP configuration region\r
   ///\r
   UINT32  CfgRegionSize;\r
   ///\r
-  /// Number of API entries this FSP supports\r
+  /// Byte 0x2C: Number of API entries this FSP supports\r
   ///\r
   UINT32  ApiEntryNum;\r
 \r
 \r
   ///\r
-  /// TempRamInit API entry offset\r
+  /// Byte 0x30: The offset for the API to setup a temporary stack till the memory\r
+  ///            is initialized.\r
   ///\r
   UINT32  TempRamInitEntryOffset;\r
   ///\r
-  /// FspInit API entry offset\r
+  /// Byte 0x34: The offset for the API to initialize the CPU and the chipset (SOC)\r
   ///\r
   UINT32  FspInitEntryOffset;\r
   ///\r
-  /// NotifyPhase API entry offset\r
+  /// Byte 0x38: The offset for the API to inform the FSP about the different stages\r
+  ///            in the boot process\r
   ///\r
   UINT32  NotifyPhaseEntryOffset;\r
+\r
   ///\r
-  /// Reserved\r
+  /// Below field is added in FSP 1.1\r
   ///\r
-  UINT32  Reserved2;\r
+\r
+  ///\r
+  /// Byte 0x3C: The offset for the API to initialize the memory\r
+  ///\r
+  UINT32  FspMemoryInitEntryOffset;\r
+  ///\r
+  /// Byte 0x40: The offset for the API to tear down temporary RAM\r
+  ///\r
+  UINT32  TempRamExitEntryOffset;\r
+  ///\r
+  /// Byte 0x44: The offset for the API to initialize the CPU and chipset\r
+  ///\r
+  UINT32  FspSiliconInitEntryOffset;\r
 \r
 } FSP_INFO_HEADER;\r
 \r
+///\r
+/// Below structure is added in FSP 1.1\r
+///\r
+typedef struct  {\r
+  ///\r
+  /// Byte 0x00: Signature ('FSPE') for the FSP Extended Information Header\r
+  ///\r
+  UINT32  Signature;\r
+  ///\r
+  /// Byte 0x04: Length of the FSP Extended Header\r
+  ///\r
+  UINT32  HeaderLength;\r
+  ///\r
+  /// Byte 0x08: Revision of the FSP Extended Header\r
+  ///\r
+  UINT8   Revision;\r
+  ///\r
+  /// Byte 0x09: Reserved for future use.\r
+  ///\r
+  UINT8   Reserved;\r
+  ///\r
+  /// Byte 0x0A: An OEM-supplied string that defines the OEM\r
+  ///\r
+  CHAR8   OemId[6];\r
+  ///\r
+  /// Byte 0x10: An OEM-supplied revision number. Larger numbers are assumed to be newer revisions.\r
+  ///\r
+  UINT32  OemRevision;\r
+\r
+} FSP_EXTENTED_HEADER;\r
+\r
 #pragma pack()\r
 \r
 #endif\r